From 827cef7f7f0f965a7706156b7d2c872ec2699805 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 30 Jan 2025 06:30:01 -0800 Subject: [PATCH] ac/gpu_info: add gfx12_supports_dcc_write_compress_disable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_gpu_info.c | 5 +++++ src/amd/common/ac_gpu_info.h | 1 + 2 files changed, 6 insertions(+) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index d1743dd30e7..204d076d2bc 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1450,6 +1450,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, */ info->gfx12_supports_display_dcc = info->gfx_level >= GFX12 && info->drm_minor >= 58; + /* AMDGPU always enables DCC compressed writes when a BO is moved back to + * VRAM until .60. + */ + info->gfx12_supports_dcc_write_compress_disable = info->gfx_level >= GFX12 && info->drm_minor >= 60; + info->has_stable_pstate = info->drm_minor >= 45; if (info->gfx_level >= GFX12) { diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 55d4a424d71..933267386c4 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -161,6 +161,7 @@ struct radeon_info { /* Allocate both aligned and unaligned DCC and use the retile blit. */ bool use_display_dcc_with_retile_blit; bool gfx12_supports_display_dcc; + bool gfx12_supports_dcc_write_compress_disable; /* Memory info. */ uint32_t pte_fragment_size;