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ilo: assorted GPE fixes for HiZ

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Allow HiZ op to be specified in 3DSTATE_WM.  Pass depth format directly in
gen7_emit_3DSTATE_SF.  Use tex->hiz.bo to determine if HiZ exists.  Fix
3DSTATE_SF for the case when there is no ilo_rasterizer_state.  Fix
3DSTATE_PS for the case when there is no ilo_shader_state.
This commit is contained in:
Chia-I Wu 2014-01-06 23:32:56 +08:00
parent 6642381e75
commit 82676f5d34
5 changed files with 67 additions and 69 deletions
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2
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
View file

@ -685,7 +685,7 @@ gen6_pipeline_wm(struct ilo_3d_pipeline *p,
gen6_wa_pipe_control_wm_max_threads_stall(p);
gen6_emit_3DSTATE_WM(p->dev, ilo->fs, num_samplers,
ilo->rasterizer, dual_blend, cc_may_kill, p->cp);
ilo->rasterizer, dual_blend, cc_may_kill, 0, p->cp);
}
}

7
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
View file

@ -462,8 +462,11 @@ gen7_pipeline_sf(struct ilo_3d_pipeline *p,
/* 3DSTATE_SF */
if (DIRTY(RASTERIZER) || DIRTY(FB)) {
struct pipe_surface *zs = ilo->fb.state.zsbuf;
gen7_wa_pipe_control_cs_stall(p, true, true);
gen7_emit_3DSTATE_SF(p->dev, ilo->rasterizer, ilo->fb.state.zsbuf, p->cp);
gen7_emit_3DSTATE_SF(p->dev, ilo->rasterizer,
(zs) ? zs->format : PIPE_FORMAT_NONE, p->cp);
}
}
@ -481,7 +484,7 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
gen7_wa_pipe_control_wm_max_threads_stall(p);
gen7_emit_3DSTATE_WM(p->dev, ilo->fs,
ilo->rasterizer, cc_may_kill, p->cp);
ilo->rasterizer, cc_may_kill, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */

15
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View file

@ -984,9 +984,8 @@ zs_init_info(const struct ilo_dev_info *dev,
unsigned first_layer, unsigned num_layers,
bool offset_to_layer, struct ilo_zs_surface_info *info)
{
struct intel_bo * const hiz_bo = NULL;
bool separate_stencil;
uint32_t x_offset[3], y_offset[3];
bool separate_stencil;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1021,7 +1020,7 @@ zs_init_info(const struct ilo_dev_info *dev,
* same value (enabled or disabled) as Hierarchical Depth Buffer
* Enable."
*/
separate_stencil = (hiz_bo != NULL);
separate_stencil = (tex->hiz.bo != NULL);
}
/*
@ -1110,10 +1109,12 @@ zs_init_info(const struct ilo_dev_info *dev,
}
}
if (hiz_bo) {
info->hiz.bo = hiz_bo;
info->hiz.stride = 0;
info->hiz.tiling = 0;
if (tex->hiz.bo) {
info->hiz.bo = tex->hiz.bo;
info->hiz.stride = tex->hiz.bo_stride;
info->hiz.tiling = INTEL_TILING_Y;
assert(!offset_to_layer);
info->hiz.offset = 0;
x_offset[2] = 0;
y_offset[2] = 0;

84
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View file

@ -209,40 +209,14 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
enum pipe_format depth_format,
uint32_t *payload, unsigned payload_len)
{
const struct ilo_rasterizer_sf *sf = &rasterizer->sf;
assert(payload_len == Elements(rasterizer->sf.payload));
assert(payload_len == Elements(sf->payload));
if (rasterizer) {
const struct ilo_rasterizer_sf *sf = &rasterizer->sf;
if (sf) {
memcpy(payload, sf->payload, sizeof(sf->payload));
if (num_samples > 1)
payload[1] |= sf->dw_msaa;
if (dev->gen >= ILO_GEN(7)) {
int format;
/* separate stencil */
switch (depth_format) {
case PIPE_FORMAT_Z16_UNORM:
format = BRW_DEPTHFORMAT_D16_UNORM;
break;
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
format = BRW_DEPTHFORMAT_D32_FLOAT;
break;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
break;
default:
/* FLOAT surface is assumed when there is no depth buffer */
format = BRW_DEPTHFORMAT_D32_FLOAT;
break;
}
payload[0] |= format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT;
}
}
else {
payload[0] = 0;
@ -252,6 +226,31 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
payload[4] = 0;
payload[5] = 0;
}
if (dev->gen >= ILO_GEN(7)) {
int format;
/* separate stencil */
switch (depth_format) {
case PIPE_FORMAT_Z16_UNORM:
format = BRW_DEPTHFORMAT_D16_UNORM;
break;
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
format = BRW_DEPTHFORMAT_D32_FLOAT;
break;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
break;
default:
/* FLOAT surface is assumed when there is no depth buffer */
format = BRW_DEPTHFORMAT_D32_FLOAT;
break;
}
payload[0] |= format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT;
}
}
/**
@ -1217,6 +1216,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
int num_samplers,
const struct ilo_rasterizer_state *rasterizer,
bool dual_blend, bool cc_may_kill,
uint32_t hiz_op,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
@ -1236,7 +1236,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, hiz_op);
/* honor the valid range even if dispatching is disabled */
ilo_cp_write(cp, (max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT);
ilo_cp_write(cp, 0);
@ -1255,21 +1255,15 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
dw2 |= (num_samplers + 3) / 4 << GEN6_WM_SAMPLER_COUNT_SHIFT;
if (true) {
dw4 |= GEN6_WM_STATISTICS_ENABLE;
}
else {
/*
* From the Sandy Bridge PRM, volume 2 part 1, page 248:
*
* "This bit (Statistics Enable) must be disabled if either of these
* bits is set: Depth Buffer Clear , Hierarchical Depth Buffer
* Resolve Enable or Depth Buffer Resolve Enable."
*/
dw4 |= GEN6_WM_DEPTH_CLEAR;
dw4 |= GEN6_WM_DEPTH_RESOLVE;
dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE;
}
/*
* From the Sandy Bridge PRM, volume 2 part 1, page 248:
*
* "This bit (Statistics Enable) must be disabled if either of these
* bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
* Enable or Depth Buffer Resolve Enable."
*/
assert(!hiz_op);
dw4 |= GEN6_WM_STATISTICS_ENABLE;
if (cc_may_kill) {
dw5 |= GEN6_WM_KILL_ENABLE |

28
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View file

@ -256,7 +256,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
static inline void
gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
const struct ilo_rasterizer_state *rasterizer,
const struct pipe_surface *zs_surf,
enum pipe_format zs_format,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
@ -267,8 +267,7 @@ gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 7, 7.5);
ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
rasterizer, num_samples,
(zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
rasterizer, num_samples, zs_format,
payload, Elements(payload));
ilo_cp_begin(cp, cmd_len);
@ -281,7 +280,7 @@ static inline void
gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
const struct ilo_shader_state *fs,
const struct ilo_rasterizer_state *rasterizer,
bool cc_may_kill,
bool cc_may_kill, uint32_t hiz_op,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
@ -292,15 +291,16 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 7, 7.5);
/* see ilo_gpe_init_rasterizer_wm() */
dw1 = rasterizer->wm.payload[0];
dw2 = rasterizer->wm.payload[1];
if (rasterizer) {
dw1 = rasterizer->wm.payload[0];
dw2 = rasterizer->wm.payload[1];
dw1 |= GEN7_WM_STATISTICS_ENABLE;
if (false) {
dw1 |= GEN7_WM_DEPTH_CLEAR;
dw1 |= GEN7_WM_DEPTH_RESOLVE;
dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
assert(!hiz_op);
dw1 |= GEN7_WM_STATISTICS_ENABLE;
}
else {
dw1 = hiz_op;
dw2 = 0;
}
if (fs) {
@ -638,12 +638,12 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
switch (dev->gen) {
case ILO_GEN(7.5):
max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
dw4 |= max_threads << HSW_PS_MAX_THREADS_SHIFT;
dw4 |= (max_threads - 1) << HSW_PS_MAX_THREADS_SHIFT;
break;
case ILO_GEN(7):
default:
max_threads = (dev->gt == 2) ? 172 : 48;
dw4 |= max_threads << IVB_PS_MAX_THREADS_SHIFT;
dw4 |= (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT;
break;
}