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OPTIONAL: iris: Perform BLORP buffer barriers outside of iris_blorp_exec() hook.
The iris_blorp_exec() hook needs to be executed under a single indivisible sync region, which means that in cases where we need to emit a PIPE_CONTROL for a buffer barrier we won't be able to track the subsequent commands separately from the previous commands, which will prevent us from optimizing out subsequent PIPE_CONTROLs if we encounter the same buffers again. In particular I've encountered this situation in some SynMark test-cases which perform lots of BLORP operations with the same buffer bound as both source and destination (in order to generate mipmaps): In such a scenario if the source requires flushing we'd also end up flushing for the destination redundantly, even though a single PIPE_CONTROL would have been sufficient. This avoids a 4.5% FPS regression in SynMark OglHdrBloom and a 3.5% FPS regression in SynMark OglMultithread. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
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4b00338bde
commit
8252bb0ec6
4 changed files with 24 additions and 15 deletions
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@ -382,6 +382,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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iris_resource_prepare_access(ice, src_res, info->src.level, 1,
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info->src.box.z, info->src.box.depth,
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src_aux_usage, src_clear_supported);
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iris_emit_buffer_barrier_for(batch, src_res->bo, IRIS_DOMAIN_OTHER_READ);
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struct iris_format_info dst_fmt =
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iris_format_for_usage(devinfo, info->dst.format,
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@ -401,6 +402,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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iris_resource_prepare_access(ice, dst_res, info->dst.level, 1,
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info->dst.box.z, info->dst.box.depth,
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dst_aux_usage, dst_clear_supported);
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iris_emit_buffer_barrier_for(batch, dst_res->bo, IRIS_DOMAIN_RENDER_WRITE);
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float src_x0 = info->src.box.x;
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float src_x1 = info->src.box.x + info->src.box.width;
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@ -527,9 +529,11 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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iris_resource_prepare_access(ice, src_res, info->src.level, 1,
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info->src.box.z, info->src.box.depth,
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stc_src_aux_usage, false);
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iris_emit_buffer_barrier_for(batch, src_res->bo, IRIS_DOMAIN_OTHER_READ);
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iris_resource_prepare_access(ice, stc_dst, info->dst.level, 1,
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info->dst.box.z, info->dst.box.depth,
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stc_dst_aux_usage, false);
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iris_emit_buffer_barrier_for(batch, stc_dst->bo, IRIS_DOMAIN_RENDER_WRITE);
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iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf,
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&src_res->base, stc_src_aux_usage,
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info->src.level, false);
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@ -664,6 +668,11 @@ iris_copy_region(struct blorp_context *blorp,
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.reloc_flags = EXEC_OBJECT_WRITE,
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};
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iris_emit_buffer_barrier_for(batch, iris_resource_bo(src),
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IRIS_DOMAIN_OTHER_READ);
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iris_emit_buffer_barrier_for(batch, iris_resource_bo(dst),
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IRIS_DOMAIN_RENDER_WRITE);
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iris_batch_maybe_flush(batch, 1500);
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iris_batch_sync_region_start(batch);
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@ -687,6 +696,11 @@ iris_copy_region(struct blorp_context *blorp,
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dstz, src_box->depth,
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dst_aux_usage, dst_clear_supported);
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iris_emit_buffer_barrier_for(batch, iris_resource_bo(src),
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IRIS_DOMAIN_OTHER_READ);
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iris_emit_buffer_barrier_for(batch, iris_resource_bo(dst),
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IRIS_DOMAIN_RENDER_WRITE);
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blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0);
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for (int slice = 0; slice < src_box->depth; slice++) {
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@ -274,27 +274,17 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
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PIPE_CONTROL_STALL_AT_SCOREBOARD);
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#endif
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/* Flush the sampler and render caches. We definitely need to flush the
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* sampler cache so that we get updated contents from the render cache for
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* the glBlitFramebuffer() source. Also, we are sometimes warned in the
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* docs to flush the cache between reinterpretations of the same surface
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* data with different formats, which blorp does for stencil and depth
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* data.
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/* Flush the render cache in cases where the same surface is reinterpreted
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* with a differernt format, which blorp does for stencil and depth data
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* among other things. Invalidation of sampler caches and flushing of any
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* caches which had previously written the source surfaces should already
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* have been handled by the caller.
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*/
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if (params->src.enabled)
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iris_emit_buffer_barrier_for(batch, params->src.addr.buffer,
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IRIS_DOMAIN_OTHER_READ);
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if (params->dst.enabled) {
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iris_cache_flush_for_render(batch, params->dst.addr.buffer,
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params->dst.view.format,
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params->dst.aux_usage);
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}
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if (params->depth.enabled)
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iris_emit_buffer_barrier_for(batch, params->depth.addr.buffer,
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IRIS_DOMAIN_DEPTH_WRITE);
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if (params->stencil.enabled)
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iris_emit_buffer_barrier_for(batch, params->stencil.addr.buffer,
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IRIS_DOMAIN_DEPTH_WRITE);
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iris_require_command_space(batch, 1400);
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@ -378,6 +378,7 @@ clear_color(struct iris_context *ice,
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iris_resource_prepare_render(ice, batch, res, level,
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box->z, box->depth, aux_usage);
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
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struct blorp_surf surf;
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iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
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@ -596,6 +597,7 @@ clear_depth_stencil(struct iris_context *ice,
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if (clear_depth && z_res) {
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iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
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iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE);
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iris_blorp_surf_for_resource(&batch->screen->isl_dev,
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&z_surf, &z_res->base, z_res->aux.usage,
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level, true);
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@ -605,6 +607,8 @@ clear_depth_stencil(struct iris_context *ice,
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if (stencil_mask) {
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iris_resource_prepare_access(ice, stencil_res, level, 1, box->z,
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box->depth, stencil_res->aux.usage, false);
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iris_emit_buffer_barrier_for(batch, stencil_res->bo,
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IRIS_DOMAIN_DEPTH_WRITE);
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iris_blorp_surf_for_resource(&batch->screen->isl_dev,
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&stencil_surf, &stencil_res->base,
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stencil_res->aux.usage, level, true);
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@ -450,6 +450,7 @@ iris_mcs_partial_resolve(struct iris_context *ice,
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struct blorp_surf surf;
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iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
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&res->base, res->aux.usage, 0, true);
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
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struct blorp_batch blorp_batch;
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iris_batch_sync_region_start(batch);
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