diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index af412492b7c..d40a4dd2db6 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -491,7 +491,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) } case nir_intrinsic_load_poly_line_smooth_enabled: { nir_def *line_rast_mode = GET_SGPR_FIELD_NIR(s->args->ps_state, PS_STATE_LINE_RAST_MODE); - replacement = nir_ieq_imm(b, line_rast_mode, VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR); + replacement = nir_ieq_imm(b, line_rast_mode, VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH); break; } case nir_intrinsic_load_initial_edgeflags_amd: diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a15e2e8e002..7ef4d0ba6d8 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1047,7 +1047,7 @@ radv_get_line_mode(const struct radv_cmd_buffer *cmd_buffer) if (draw_lines) return d->vk.rs.line.mode; - return VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT; + return VK_LINE_RASTERIZATION_MODE_DEFAULT; } static ALWAYS_INLINE unsigned @@ -1057,7 +1057,7 @@ radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) VkLineRasterizationModeEXT line_mode = radv_get_line_mode(cmd_buffer); - if (line_mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_KHR) { + if (line_mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM) { /* From the Vulkan spec 1.3.221: * * "When Bresenham lines are being rasterized, sample locations may all be treated as being at @@ -1070,7 +1070,7 @@ radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) return 1; } - if (line_mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR) { + if (line_mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH) { return RADV_NUM_SMOOTH_AA_SAMPLES; } @@ -5445,7 +5445,7 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer) S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); } - if (radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR) + if (radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH) db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples); } @@ -8154,7 +8154,7 @@ radv_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer, const VkSampleLocat } VKAPI_ATTR void VKAPI_CALL -radv_CmdSetLineStippleKHR(VkCommandBuffer commandBuffer, uint32_t lineStippleFactor, uint16_t lineStipplePattern) +radv_CmdSetLineStipple(VkCommandBuffer commandBuffer, uint32_t lineStippleFactor, uint16_t lineStipplePattern) { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; @@ -8668,7 +8668,7 @@ radv_CmdSetRasterizationSamplesEXT(VkCommandBuffer commandBuffer, VkSampleCountF } VKAPI_ATTR void VKAPI_CALL -radv_CmdSetLineRasterizationModeEXT(VkCommandBuffer commandBuffer, VkLineRasterizationModeKHR lineRasterizationMode) +radv_CmdSetLineRasterizationModeEXT(VkCommandBuffer commandBuffer, VkLineRasterizationMode lineRasterizationMode) { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; @@ -10495,8 +10495,8 @@ radv_emit_db_shader_control(struct radv_cmd_buffer *cmd_buffer) * correct value. * Also apply the bug workaround for smoothing (overrasterization) on GFX6. */ - if (uses_ds_feedback_loop || (gpu_info->gfx_level == GFX6 && - radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR)) + if (uses_ds_feedback_loop || + (gpu_info->gfx_level == GFX6 && radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH)) db_shader_control = (db_shader_control & C_02880C_Z_ORDER) | S_02880C_Z_ORDER(V_02880C_LATE_Z); if (ps && ps->info.ps.pops) { @@ -10726,7 +10726,7 @@ radv_emit_raster_state(struct radv_cmd_buffer *cmd_buffer) */ radeon_opt_set_context_reg( cmd_buffer, R_028BDC_PA_SC_LINE_CNTL, RADV_TRACKED_PA_SC_LINE_CNTL, - S_028BDC_PERPENDICULAR_ENDCAP_ENA(radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_KHR)); + S_028BDC_PERPENDICULAR_ENDCAP_ENA(radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR)); const bool depth_clip_enable = radv_get_depth_clip_enable(cmd_buffer); @@ -10752,7 +10752,7 @@ radv_emit_raster_state(struct radv_cmd_buffer *cmd_buffer) */ pa_su_sc_mode_cntl |= S_028814_KEEP_TOGETHER_ENABLE(d->vk.rs.polygon_mode != V_028814_X_DRAW_TRIANGLES || - radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_KHR); + radv_get_line_mode(cmd_buffer) == VK_LINE_RASTERIZATION_MODE_RECTANGULAR); } if (pdev->info.gfx_level >= GFX12) { diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 3f8f42c8579..a12272d99fe 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -295,7 +295,7 @@ radv_dynamic_state_mask(VkDynamicState state) return RADV_DYNAMIC_DISCARD_RECTANGLE; case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT: return RADV_DYNAMIC_SAMPLE_LOCATIONS; - case VK_DYNAMIC_STATE_LINE_STIPPLE_KHR: + case VK_DYNAMIC_STATE_LINE_STIPPLE: return RADV_DYNAMIC_LINE_STIPPLE; case VK_DYNAMIC_STATE_CULL_MODE: return RADV_DYNAMIC_CULL_MODE; @@ -1964,7 +1964,7 @@ radv_generate_graphics_state_key(const struct radv_device *device, const struct * simplifies the implementation. */ if (BITSET_TEST(state->dynamic, MESA_VK_DYNAMIC_RS_LINE_MODE) || - (state->rs && state->rs->line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR)) + (state->rs && state->rs->line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH)) key.dynamic_line_rast_mode = true; /* For GPL, when the fragment shader is compiled without any pre-rasterization information,