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intel/compiler: Move earlier scheduler code that is not mode-specific

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This will be useful later on when we reuse the same scheduler for
multiple modes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25841>
This commit is contained in:
Caio Oliveira 2023-10-20 09:45:14 -07:00 • committed by Marge Bot
parent 73d4e4118a
commit 81594d0db1
1 changed files with 15 additions and 15 deletions
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30
src/intel/compiler/brw_schedule_instructions.cpp
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@ -815,6 +815,8 @@ fs_instruction_scheduler::fs_instruction_scheduler(const fs_visitor *v,
this->hw_liveout[i] = linear_zalloc_array(lin_ctx, BITSET_WORD,
BITSET_WORDS(hw_reg_count));
setup_liveness(v->cfg);
this->written = linear_alloc_array(lin_ctx, bool, grf_count);
this->reads_remaining = linear_alloc_array(lin_ctx, int, grf_count);
@ -829,6 +831,17 @@ fs_instruction_scheduler::fs_instruction_scheduler(const fs_visitor *v,
this->reads_remaining = NULL;
this->hw_reads_remaining = NULL;
}
foreach_block(block, v->cfg) {
set_current_block(block);
for (schedule_node *n = current.start; n < current.end; n++)
n->issue_time = calculate_issue_time(n->inst);
calculate_deps();
compute_delays();
compute_exits();
}
}
static bool
@ -1937,8 +1950,6 @@ fs_instruction_scheduler::run()
}
if (!post_reg_alloc) {
setup_liveness(v->cfg);
memset(reads_remaining, 0, grf_count * sizeof(*reads_remaining));
memset(hw_reads_remaining, 0, hw_reg_count * sizeof(*hw_reads_remaining));
memset(written, 0, grf_count * sizeof(*written));
@ -1947,17 +1958,11 @@ fs_instruction_scheduler::run()
foreach_block(block, v->cfg) {
set_current_block(block);
for (schedule_node *n = current.start; n < current.end; n++) {
if (!post_reg_alloc)
if (!post_reg_alloc) {
for (schedule_node *n = current.start; n < current.end; n++)
count_reads_remaining(n->inst);
n->issue_time = calculate_issue_time(n->inst);
}
calculate_deps();
compute_delays();
compute_exits();
schedule_instructions();
}
@ -1979,11 +1984,6 @@ vec4_instruction_scheduler::run()
n->issue_time = 2;
}
calculate_deps();
compute_delays();
compute_exits();
/* Add DAG heads to the list of available instructions. */
assert(current.available.is_empty());
for (schedule_node *n = current.start; n < current.end; n++) {