diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 2e81e0cff97..cd0f0da49a1 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -3504,6 +3504,7 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
           * WSI blit source, keep compression as we can do a compressed to
           * uncompressed copy.
           */
+         assert(devinfo->ver <= 11);
          if (image->wsi_blit_src)
             return ISL_AUX_STATE_COMPRESSED_CLEAR;
 
@@ -3541,9 +3542,16 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
       vk_image_layout_to_usage_flags(layout, aspect) & image_aspect_usage;
 
    bool aux_supported = true;
-   bool clear_supported = isl_aux_usage_has_fast_clears(aux_usage);
    bool hiz_supported = isl_aux_usage_has_hiz(aux_usage);
 
+   /* Whether or not a CLEAR state is supported. On Xe2+, HSD 14011946253 and
+    * the related documents explain that MCS continues to use the CLEAR state
+    * like prior platforms.
+    */
+   bool clear_supported = isl_aux_usage_has_fast_clears(aux_usage) &&
+                          (devinfo->ver < 20 ||
+                           isl_aux_usage_has_mcs(aux_usage));
+
    if ((usage & (VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
                  VK_IMAGE_USAGE_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT)) &&
        !read_only) {
@@ -3615,9 +3623,10 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
       if (hiz_supported && aux_usage != ISL_AUX_USAGE_HIZ_CCS_WT) {
          assert(aux_supported);
          return ISL_AUX_STATE_COMPRESSED_HIER_DEPTH;
-      } else if (aux_supported) {
-         assert(clear_supported);
+      } else if (clear_supported) {
          return ISL_AUX_STATE_COMPRESSED_CLEAR;
+      } else if (aux_supported) {
+         return ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
       } else if (read_only) {
          return ISL_AUX_STATE_RESOLVED;
       } else {
@@ -3637,13 +3646,6 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
 
    case ISL_AUX_USAGE_CCS_E:
    case ISL_AUX_USAGE_FCV_CCS_E:
-      if (aux_supported) {
-         assert(clear_supported);
-         return ISL_AUX_STATE_COMPRESSED_CLEAR;
-      } else {
-         return ISL_AUX_STATE_PASS_THROUGH;
-      }
-
    case ISL_AUX_USAGE_MCS:
    case ISL_AUX_USAGE_MCS_CCS:
       assert(aux_supported);
@@ -3776,18 +3778,6 @@ anv_layout_to_fast_clear_type(const struct intel_device_info * const devinfo,
    if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
       return ANV_FAST_CLEAR_NONE;
 
-   /* Bspec 57340 (r68483) has no fast-clear rectangle for linear surfaces. */
-   if (image->planes[plane].primary_surface.isl.tiling == ISL_TILING_LINEAR) {
-      assert(devinfo->ver >= 20);
-      return ANV_FAST_CLEAR_NONE;
-   }
-
-   /* Xe2+ platforms don't have fast clear type and can always support
-    * arbitrary fast-clear values.
-    */
-   if (devinfo->ver >= 20)
-      return ANV_FAST_CLEAR_ANY;
-
    enum isl_aux_state aux_state =
       anv_layout_to_aux_state(devinfo, image, aspect, layout, queue_flags);
 
@@ -3806,15 +3796,15 @@ anv_layout_to_fast_clear_type(const struct intel_device_info * const devinfo,
    case ISL_AUX_STATE_PARTIAL_CLEAR:
    case ISL_AUX_STATE_COMPRESSED_CLEAR:
 
-      /* Generally, enabling non-zero fast-clears is dependent on knowing which
-       * formats will be used with the surface. So, disable them if we lack
-       * this knowledge.
+      /* On gfx12 and prior, enabling non-zero fast-clears is dependent on
+       * knowing which formats will be used with the surface. So, disable them
+       * if we lack this knowledge.
        *
        * For dmabufs with clear color modifiers, we already restrict
        * problematic accesses for the clear color during the negotiation
        * phase. So, don't restrict clear color support in this case.
        */
-      if (anv_image_view_formats_incomplete(image) &&
+      if (devinfo->ver <= 12 && anv_image_view_formats_incomplete(image) &&
           !(isl_mod_info && isl_mod_info->supports_clear_color)) {
          return ANV_FAST_CLEAR_DEFAULT_VALUE;
       }
@@ -3847,7 +3837,17 @@ anv_layout_to_fast_clear_type(const struct intel_device_info * const devinfo,
    case ISL_AUX_STATE_RESOLVED:
    case ISL_AUX_STATE_PASS_THROUGH:
    case ISL_AUX_STATE_AUX_INVALID:
-      return ANV_FAST_CLEAR_NONE;
+      if (devinfo->ver >= 20 &&
+          image->planes[plane].primary_surface.isl.tiling !=
+          ISL_TILING_LINEAR) {
+         /* Xe2+ can fast-clear without a CLEAR state. It just needs a
+          * supported tiling. Bspec 57340 (r68483) only has fast-clear
+          * rectangles for Tile4 and Tile64.
+          */
+         return ANV_FAST_CLEAR_ANY;
+      } else {
+         return ANV_FAST_CLEAR_NONE;
+      }
    }
 
    UNREACHABLE("Invalid isl_aux_state");