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ir3: Suppress disasm of internal shaders unless IR3_SHADER_DEBUG=internal.

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When you're debugging some deqp test or app, it's irritating to page
through 8 MRT clear shaders in turnip to get to what you're looking for.
Use the info.internal flag to suppress those shaders.  (but if you want to
IR3_SHADER_DEBUG=internal, then yeah, print them all).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18002>
This commit is contained in:
Emma Anholt 2022-08-09 10:58:35 -07:00 • committed by Marge Bot
parent ad274ba889
commit 8116839db9
6 changed files with 19 additions and 9 deletions
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1
src/freedreno/ir3/ir3_compiler.c
View file

@ -38,6 +38,7 @@ static const struct debug_named_value shader_debug_options[] = {
{"gs", IR3_DBG_SHADER_GS, "Print shader disasm for geometry shaders"},
{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
{"internal", IR3_DBG_SHADER_INTERNAL, "Print shader disasm for internal shaders (normally not included in vs/fs/cs/etc)"},
{"disasm", IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
{"optmsgs", IR3_DBG_OPTMSGS, "Enable optimizer debug messages"},
{"forces2en", IR3_DBG_FORCES2EN, "Force s2en mode for tex sampler instructions"},

6
src/freedreno/ir3/ir3_compiler.h
View file

@ -266,6 +266,7 @@ enum ir3_shader_debug {
IR3_DBG_NOCACHE = BITFIELD_BIT(11),
IR3_DBG_SPILLALL = BITFIELD_BIT(12),
IR3_DBG_NOPREAMBLE = BITFIELD_BIT(13),
IR3_DBG_SHADER_INTERNAL = BITFIELD_BIT(14),
/* DEBUG-only options: */
IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20),
@ -279,8 +280,11 @@ extern enum ir3_shader_debug ir3_shader_debug;
extern const char *ir3_shader_override_path;
static inline bool
shader_debug_enabled(gl_shader_stage type)
shader_debug_enabled(gl_shader_stage type, bool internal)
{
if (internal)
return !!(ir3_shader_debug & IR3_DBG_SHADER_INTERNAL);
if (ir3_shader_debug & IR3_DBG_DISASM)
return true;

2
src/freedreno/ir3/ir3_context.c
View file

@ -154,7 +154,7 @@ ir3_context_init(struct ir3_compiler *compiler, struct ir3_shader *shader,
}
}
if (shader_debug_enabled(so->type)) {
if (shader_debug_enabled(so->type, ctx->s->info.internal)) {
mesa_logi("NIR (final form) for %s shader %s:", ir3_shader_stage(so),
so->name);
nir_log_shaderi(ctx->s);

8
src/freedreno/ir3/ir3_nir_lower_tess.c
View file

@ -670,7 +670,7 @@ ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
{
struct state state = {.topology = topology};
if (shader_debug_enabled(shader->info.stage)) {
if (shader_debug_enabled(shader->info.stage, shader->info.internal)) {
mesa_logi("NIR (before tess lowering) for %s shader:",
_mesa_shader_stage_to_string(shader->info.stage));
nir_log_shaderi(shader);
@ -828,7 +828,7 @@ ir3_nir_lower_tess_eval(nir_shader *shader, struct ir3_shader_variant *v,
{
struct state state = {.topology = topology};
if (shader_debug_enabled(shader->info.stage)) {
if (shader_debug_enabled(shader->info.stage, shader->info.internal)) {
mesa_logi("NIR (before tess lowering) for %s shader:",
_mesa_shader_stage_to_string(shader->info.stage));
nir_log_shaderi(shader);
@ -929,7 +929,7 @@ ir3_nir_lower_gs(nir_shader *shader)
if (var->data.location == VARYING_SLOT_GS_VERTEX_FLAGS_IR3)
return;
if (shader_debug_enabled(shader->info.stage)) {
if (shader_debug_enabled(shader->info.stage, shader->info.internal)) {
mesa_logi("NIR (before gs lowering):");
nir_log_shaderi(shader);
}
@ -1045,7 +1045,7 @@ ir3_nir_lower_gs(nir_shader *shader)
nir_fixup_deref_modes(shader);
if (shader_debug_enabled(shader->info.stage)) {
if (shader_debug_enabled(shader->info.stage, shader->info.internal)) {
mesa_logi("NIR (after gs lowering):");
nir_log_shaderi(shader);
}

6
src/freedreno/ir3/ir3_shader.c
View file

@ -229,11 +229,11 @@ try_override_shader_variant(struct ir3_shader_variant *v,
}
static void
assemble_variant(struct ir3_shader_variant *v)
assemble_variant(struct ir3_shader_variant *v, bool internal)
{
v->bin = ir3_shader_assemble(v);
bool dbg_enabled = shader_debug_enabled(v->type);
bool dbg_enabled = shader_debug_enabled(v->type, internal);
if (dbg_enabled || ir3_shader_override_path || v->disasm_info.write_disasm) {
unsigned char sha1[21];
char sha1buf[41];
@ -297,7 +297,7 @@ compile_variant(struct ir3_shader *shader, struct ir3_shader_variant *v)
return false;
}
assemble_variant(v);
assemble_variant(v, shader->nir->info.internal);
if (!v->bin) {
mesa_loge("assemble failed! (%s:%s)", shader->nir->info.name,
shader->nir->info.label);

5
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -432,6 +432,7 @@ build_blit_vs_shader(void)
nir_builder _b =
nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "blit vs");
nir_builder *b = &_b;
b->shader->info.internal = true;
nir_variable *out_pos =
nir_variable_create(b->shader, nir_var_shader_out, glsl_vec4_type(),
@ -476,6 +477,7 @@ build_clear_vs_shader(void)
nir_builder _b =
nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "blit vs");
nir_builder *b = &_b;
b->shader->info.internal = true;
nir_variable *out_pos =
nir_variable_create(b->shader, nir_var_shader_out, glsl_vec4_type(),
@ -512,6 +514,7 @@ build_blit_fs_shader(bool zscale)
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL,
zscale ? "zscale blit fs" : "blit fs");
nir_builder *b = &_b;
b->shader->info.internal = true;
nir_variable *out_color =
nir_variable_create(b->shader, nir_var_shader_out, glsl_vec4_type(),
@ -562,6 +565,7 @@ build_ms_copy_fs_shader(void)
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL,
"multisample copy fs");
nir_builder *b = &_b;
b->shader->info.internal = true;
nir_variable *out_color =
nir_variable_create(b->shader, nir_var_shader_out, glsl_vec4_type(),
@ -617,6 +621,7 @@ build_clear_fs_shader(unsigned mrts)
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL,
"mrt%u clear fs", mrts);
nir_builder *b = &_b;
b->shader->info.internal = true;
for (unsigned i = 0; i < mrts; i++) {
nir_variable *out_color =