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etnaviv: Support opcodes with bit 6 set in assembler

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Support opcodes with bit 6 set in assembler, and assert that only ops
0x00..0x7f are used.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit is contained in:
Wladimir J. van der Laan 2017-10-01 11:21:19 +02:00 • committed by Christian Gmeiner
parent df82012b2c
commit 80f608b530
1 changed files with 4 additions and 1 deletions
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5
src/gallium/drivers/etnaviv/etnaviv_asm.c
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@ -68,7 +68,9 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst)
if (!check_uniforms(inst))
BUG("error: generating instruction that accesses two different uniforms");
out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode) |
assert(!(inst->opcode&~0x7f));
out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode & 0x3f) |
VIV_ISA_WORD_0_COND(inst->cond) |
COND(inst->sat, VIV_ISA_WORD_0_SAT) |
COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |
@ -88,6 +90,7 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst)
VIV_ISA_WORD_2_SRC0_RGROUP(inst->src[0].rgroup) |
COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |
VIV_ISA_WORD_2_SRC1_REG(inst->src[1].reg) |
COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) |
VIV_ISA_WORD_2_SRC1_SWIZ(inst->src[1].swiz) |
COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) |
COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) |