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radeonsi/sqtt: re-export shaders in a single bo
RGP expects a pipeline's shaders to be all stored sequentially, eg: [vs][ps][gs] As such, it assumes a single bo is dumped to the .rgp file, with the following info: * va of the bo * offset to each shader inside the bo For radeonsi, the shaders are stored individually, so we may have a big gap between the shaders forming a pipeline => we can produce very large file because the layout in the file must match the one in memory (see the warning in ac_rgp_file_write_elf_text). This commit implements a workaround: gfx shaders are re-exported as a pipeline. To update the shader address, a new state is created (sqtt_pipeline), which will overwrite the needed _PGM_LO_* registers. This reduces DeuxEX rgp captures from 150GB+ to less than 100MB. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18865>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
Marge Bot
parent
5a9a43c8f9
commit
8034a71430
10 changed files with 151 additions and 23 deletions
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@ -53,6 +53,8 @@ struct ac_thread_trace_data {
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struct rgp_queue_event rgp_queue_event;
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struct rgp_clock_calibration rgp_clock_calibration;
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struct hash_table_u64 *pipeline_bos;
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};
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#define SQTT_BUFFER_ALIGN_SHIFT 12
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@ -320,11 +320,18 @@ static void si_bind_compute_state(struct pipe_context *ctx, void *state)
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program->shader.binary.elf_buffer,
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program->shader.binary.elf_size,
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0);
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uint64_t base_address = program->shader.bo->gpu_address;
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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if (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_code_hash)) {
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si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, true);
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/* Short lived fake pipeline: we don't need to reupload the compute shaders,
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* as we do for the gfx ones so just create a temp pipeline to be able to
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* call si_sqtt_register_pipeline, and then drop it.
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*/
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struct si_sqtt_fake_pipeline pipeline = { 0 };
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pipeline.code_hash = pipeline_code_hash;
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pipeline.bo = program->shader.bo;
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si_sqtt_register_pipeline(sctx, &pipeline, true);
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}
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si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
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@ -912,6 +912,13 @@ struct si_saved_cs {
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int64_t time_flush;
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};
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struct si_sqtt_fake_pipeline {
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struct si_pm4_state pm4; /* base class */
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uint64_t code_hash;
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struct si_resource *bo;
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uint32_t offset[SI_NUM_GRAPHICS_SHADERS];
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};
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struct si_small_prim_cull_info {
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float scale[2], translate[2];
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float scale_no_aa[2], translate_no_aa[2];
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@ -1646,7 +1653,7 @@ void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *r
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uint32_t vertex_offset_user_data,
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uint32_t instance_offset_user_data,
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uint32_t draw_index_user_data);
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bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute);
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bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline, bool is_compute);
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bool si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data,
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uint64_t pipeline_hash);
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void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
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@ -55,6 +55,9 @@ struct si_pm4_state {
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/* commands for the DE */
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uint16_t max_dw;
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/* Used by SQTT to override the shader address */
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uint16_t reg_va_low_idx;
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/* This must be the last field because the array can continue after the structure. */
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uint32_t pm4[64];
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};
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@ -817,8 +817,8 @@ static unsigned get_lds_granularity(struct si_screen *screen, gl_shader_stage st
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screen->info.gfx_level >= GFX7 ? 512 : 256;
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}
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static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *shader,
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struct ac_rtld_binary *rtld)
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bool si_shader_binary_open(struct si_screen *screen, struct si_shader *shader,
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struct ac_rtld_binary *rtld)
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{
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const struct si_shader_selector *sel = shader->selector;
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const char *part_elfs[5];
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@ -889,8 +889,8 @@ static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_sh
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return size;
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}
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static bool si_get_external_symbol(enum amd_gfx_level gfx_level, void *data, const char *name,
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uint64_t *value)
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bool si_get_external_symbol(enum amd_gfx_level gfx_level, void *data, const char *name,
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uint64_t *value)
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{
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uint64_t *scratch_va = data;
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@ -960,6 +960,8 @@ struct si_shader_part {
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};
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/* si_shader.c */
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struct ac_rtld_binary;
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void si_update_shader_binary_info(struct si_shader *shader, nir_shader *nir);
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bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
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struct si_shader *shader, struct util_debug_callback *debug);
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@ -979,6 +981,10 @@ const char *si_get_shader_name(const struct si_shader *shader);
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void si_shader_binary_clean(struct si_shader_binary *binary);
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struct nir_shader *si_deserialize_shader(struct si_shader_selector *sel);
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unsigned si_get_ps_num_interp(struct si_shader *ps);
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bool si_shader_binary_open(struct si_screen *screen, struct si_shader *shader,
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struct ac_rtld_binary *rtld);
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bool si_get_external_symbol(enum amd_gfx_level gfx_level, void *data, const char *name,
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uint64_t *value);
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/* si_shader_info.c */
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void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
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@ -24,6 +24,7 @@
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*/
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#include "hash_table.h"
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#include "si_pipe.h"
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#include "si_build_pm4.h"
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#include "si_compute.h"
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@ -55,6 +56,8 @@ si_thread_trace_init_bo(struct si_context *sctx)
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1 << SQTT_BUFFER_ALIGN_SHIFT);
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size += sctx->thread_trace->buffer_size * (uint64_t)max_se;
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sctx->thread_trace->pipeline_bos = _mesa_hash_table_u64_create(NULL);
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sctx->thread_trace->bo =
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ws->buffer_create(ws, size, 4096,
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RADEON_DOMAIN_VRAM,
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@ -697,6 +700,12 @@ si_destroy_thread_trace(struct si_context *sctx)
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}
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simple_mtx_destroy(&sctx->thread_trace->rgp_code_object.lock);
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hash_table_foreach(sctx->thread_trace->pipeline_bos->table, entry) {
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struct si_sqtt_fake_pipeline *pipeline = (struct si_sqtt_fake_pipeline *)entry->data;
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si_resource_reference(&pipeline->bo, NULL);
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FREE(pipeline);
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}
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free(sctx->thread_trace);
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sctx->thread_trace = NULL;
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@ -1010,7 +1019,7 @@ si_sqtt_pipe_to_rgp_shader_stage(union si_shader_key* key, enum pipe_shader_type
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static bool
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si_sqtt_add_code_object(struct si_context* sctx,
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uint64_t pipeline_hash,
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struct si_sqtt_fake_pipeline *pipeline,
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bool is_compute)
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{
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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@ -1023,8 +1032,8 @@ si_sqtt_add_code_object(struct si_context* sctx,
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record->shader_stages_mask = 0;
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record->num_shaders_combined = 0;
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record->pipeline_hash[0] = pipeline_hash;
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record->pipeline_hash[1] = pipeline_hash;
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record->pipeline_hash[0] = pipeline->code_hash;
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record->pipeline_hash[1] = pipeline->code_hash;
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for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++) {
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struct si_shader *shader;
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@ -1051,7 +1060,7 @@ si_sqtt_add_code_object(struct si_context* sctx,
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}
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memcpy(code, shader->binary.uploaded_code, shader->binary.uploaded_code_size);
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uint64_t va = shader->bo->gpu_address;
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uint64_t va = pipeline->bo->gpu_address + pipeline->offset[i];
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unsigned gl_shader_stage = tgsi_processor_to_shader_stage(i);
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record->shader_data[gl_shader_stage].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size);
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record->shader_data[gl_shader_stage].hash[1] = record->shader_data[gl_shader_stage].hash[0];
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@ -1079,21 +1088,21 @@ si_sqtt_add_code_object(struct si_context* sctx,
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}
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bool
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si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute)
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si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline, bool is_compute)
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{
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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assert (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_hash));
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assert (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline->code_hash));
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bool result = ac_sqtt_add_pso_correlation(thread_trace_data, pipeline_hash);
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bool result = ac_sqtt_add_pso_correlation(thread_trace_data, pipeline->code_hash);
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if (!result)
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return false;
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result = ac_sqtt_add_code_object_loader_event(thread_trace_data, pipeline_hash, base_address);
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result = ac_sqtt_add_code_object_loader_event(thread_trace_data, pipeline->code_hash, pipeline->bo->gpu_address);
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if (!result)
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return false;
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return si_sqtt_add_code_object(sctx, pipeline_hash, is_compute);
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return si_sqtt_add_code_object(sctx, pipeline, is_compute);
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}
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void
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@ -187,6 +187,7 @@ union si_state {
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struct si_pm4_state *vgt_shader_config;
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struct si_shader *vs;
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struct si_shader *ps;
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struct si_sqtt_fake_pipeline *sqtt_pipeline;
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} named;
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struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)];
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};
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@ -29,6 +29,8 @@
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#include "util/u_index_modify.h"
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#include "util/u_prim.h"
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#include "util/u_upload_mgr.h"
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#include "ac_rtld.h"
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#include "si_build_pm4.h"
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#if (GFX_VER == 6)
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#define GFX(name) name##GFX6
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@ -303,28 +305,107 @@ static bool si_update_shaders(struct si_context *sctx)
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}
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if (unlikely(sctx->screen->debug_flags & DBG(SQTT) && sctx->thread_trace)) {
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/* Pretend the bound shaders form a vk pipeline */
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uint32_t pipeline_code_hash = 0;
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uint64_t base_address = ~0;
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/* Pretend the bound shaders form a vk pipeline. Include the scratch size in
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* the hash calculation to force re-emitting the pipeline if the scratch bo
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* changes.
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*/
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uint64_t scratch_bo_size = sctx->scratch_buffer ? sctx->scratch_buffer->bo_size : 0;
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uint64_t pipeline_code_hash = scratch_bo_size;
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uint32_t total_size = 0;
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/* Compute pipeline code hash. */
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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pipeline_code_hash = _mesa_hash_data_with_seed(
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pipeline_code_hash = XXH64(
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shader->binary.elf_buffer,
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shader->binary.elf_size,
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pipeline_code_hash);
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base_address = MIN2(base_address,
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shader->bo->gpu_address);
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total_size += ALIGN(shader->binary.uploaded_code_size, 256);
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}
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}
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struct si_sqtt_fake_pipeline *pipeline = NULL;
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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if (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_code_hash)) {
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si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, false);
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/* This is a new pipeline. Allocate a new bo to hold all the shaders. Without
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* this, shader code export process creates huge rgp files because RGP assumes
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* the shaders live sequentially in memory (shader N address = shader 0 + offset N)
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*/
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struct si_resource *bo = si_aligned_buffer_create(
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&sctx->screen->b,
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(sctx->screen->info.cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY) |
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SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
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PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
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char *ptr = (char *) (bo ? sctx->screen->ws->buffer_map(sctx->screen->ws,
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bo->buf, NULL,
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(enum pipe_map_flags)(PIPE_MAP_READ_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY)) :
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NULL);
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uint32_t offset = 0;
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uint64_t scratch_va = sctx->scratch_buffer ? sctx->scratch_buffer->gpu_address : 0;
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if (ptr) {
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pipeline = (struct si_sqtt_fake_pipeline *)
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CALLOC(1, sizeof(struct si_sqtt_fake_pipeline));
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pipeline->code_hash = pipeline_code_hash;
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si_resource_reference(&pipeline->bo, bo);
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/* Re-upload all gfx shaders and init PM4. */
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si_pm4_clear_state(&pipeline->pm4);
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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struct ac_rtld_binary binary;
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si_shader_binary_open(sctx->screen, shader, &binary);
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struct ac_rtld_upload_info u = {};
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u.binary = &binary;
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u.get_external_symbol = si_get_external_symbol;
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u.cb_data = &scratch_va;
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u.rx_va = bo->gpu_address + offset;
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u.rx_ptr = ptr + offset;
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int size = ac_rtld_upload(&u);
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ac_rtld_close(&binary);
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pipeline->offset[i] = offset;
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offset += align(size, 256);
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struct si_pm4_state *pm4 = &shader->pm4;
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uint32_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8;
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assert(PKT3_IT_OPCODE_G(pm4->pm4[pm4->reg_va_low_idx - 2]) == PKT3_SET_SH_REG);
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uint32_t reg = (pm4->pm4[pm4->reg_va_low_idx - 1] << 2) + SI_SH_REG_OFFSET;
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si_pm4_set_reg(&pipeline->pm4, reg, va_low);
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}
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}
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sctx->screen->ws->buffer_unmap(sctx->screen->ws, bo->buf);
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_mesa_hash_table_u64_insert(sctx->thread_trace->pipeline_bos,
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pipeline_code_hash, pipeline);
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si_sqtt_register_pipeline(sctx, pipeline, false);
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} else {
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if (bo)
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si_resource_reference(&bo, NULL);
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}
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} else {
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pipeline = (struct si_sqtt_fake_pipeline *)
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_mesa_hash_table_u64_search(sctx->thread_trace->pipeline_bos, pipeline_code_hash);
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}
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assert(pipeline);
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pipeline->code_hash = pipeline_code_hash;
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, pipeline->bo,
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RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
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si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
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si_pm4_bind_state(sctx, sqtt_pipeline, pipeline);
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}
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if ((GFX_VERSION <= GFX8 &&
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@ -695,6 +695,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
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va = shader->bo->gpu_address;
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si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
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pm4->reg_va_low_idx = pm4->ndw - 1;
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shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
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S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
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@ -729,6 +730,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
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} else {
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si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
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}
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pm4->reg_va_low_idx = pm4->ndw - 1;
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unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
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@ -741,6 +743,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
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shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
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} else {
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si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
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pm4->reg_va_low_idx = pm4->ndw - 1;
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si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS,
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S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8));
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||||
|
||||
|
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@ -816,6 +819,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
|
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oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
|
||||
|
||||
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
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pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES,
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S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
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||||
si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
|
||||
|
|
@ -1104,6 +1108,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
|
|||
} else {
|
||||
si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
|
||||
}
|
||||
pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
|
||||
uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
|
||||
S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
|
||||
|
|
@ -1149,6 +1154,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
|
|||
S_00B21C_WAVE_LIMIT(0x3F);
|
||||
|
||||
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
|
||||
pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS,
|
||||
S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8));
|
||||
|
||||
|
|
@ -1421,6 +1427,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
|
|||
&late_alloc_wave64, &cu_mask);
|
||||
|
||||
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
|
||||
pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
si_pm4_set_reg(
|
||||
pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
|
||||
S_00B228_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) |
|
||||
|
|
@ -1733,6 +1740,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
|
|||
}
|
||||
|
||||
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
|
||||
pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS,
|
||||
S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8));
|
||||
|
||||
|
|
@ -2008,6 +2016,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
|
|||
|
||||
va = shader->bo->gpu_address;
|
||||
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
|
||||
pm4->reg_va_low_idx = pm4->ndw - 1;
|
||||
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS,
|
||||
S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8));
|
||||
|
||||
|
|
@ -2078,6 +2087,9 @@ static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader
|
|||
default:
|
||||
assert(0);
|
||||
}
|
||||
|
||||
if (unlikely(sscreen->debug_flags & DBG(SQTT)))
|
||||
assert(shader->pm4.reg_va_low_idx != 0);
|
||||
}
|
||||
|
||||
static void si_clear_vs_key_inputs(struct si_context *sctx, union si_shader_key *key,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue