fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-30 10:00:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

r600g: code cleanup (indent, trailing space, empty line ...)

Browse source 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Jerome Glisse 2010-11-17 17:20:59 -05:00
parent 9935fe705d
commit 7ffd4e976f
9 changed files with 70 additions and 73 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/gallium/drivers/r600/evergreen_state.c
View file

@ -660,7 +660,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(1) |
S_028C70_NUMBER_TYPE(ntype);
if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
color_info |= S_028C70_SOURCE_FORMAT(1);
/* FIXME handle enabling of CB beyond BASE8 which has different offset */
@ -1467,8 +1467,8 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
S_0286E0_PERSP_CENTROID_ENA(have_centroid);
if (have_linear)
spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
spi_ps_in_control_0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,

16
src/gallium/drivers/r600/r600_asm.c
View file

@ -55,8 +55,8 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
return 2;
return 2;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
@ -74,7 +74,7 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
};
return 3;
}
@ -199,9 +199,9 @@ const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
SQ_ALU_VEC_012}; //111
const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
SQ_ALU_SCL_122, //001
SQ_ALU_SCL_122, //001
SQ_ALU_SCL_122, //010
SQ_ALU_SCL_221, //011
SQ_ALU_SCL_212, //100
SQ_ALU_SCL_122, //101
@ -678,8 +678,8 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
}
if (alu->last) {
if (alu->nliteral && !alu->literal_added) {
@ -766,7 +766,7 @@ int r600_bc_build(struct r600_bc *bc)
int r;
if (bc->callstack[0].max > 0)
bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
/* first path compute addr of each CF block */
/* addr start after all the CF instructions */

14
src/gallium/drivers/r600/r600_asm.h
View file

@ -145,12 +145,12 @@ struct r600_bc_cf {
struct r600_bc_alu *curr_bs_head;
};
#define FC_NONE 0
#define FC_IF 1
#define FC_LOOP 2
#define FC_REP 3
#define FC_PUSH_VPM 4
#define FC_PUSH_WQM 5
#define FC_NONE 0
#define FC_IF 1
#define FC_LOOP 2
#define FC_REP 3
#define FC_PUSH_VPM 4
#define FC_PUSH_WQM 5
struct r600_cf_stack_entry {
int type;
@ -166,7 +166,7 @@ struct r600_cf_callstack {
int current;
int max;
};
struct r600_bc {
enum radeon_family family;
int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */

7
src/gallium/drivers/r600/r600_blit.c
View file

@ -27,9 +27,9 @@
enum r600_blitter_op /* bitmask */
{
R600_CLEAR = 1,
R600_CLEAR_SURFACE = 2,
R600_COPY = 4
R600_CLEAR = 1,
R600_CLEAR_SURFACE = 2,
R600_COPY = 4
};
static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op)
@ -189,7 +189,6 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
else
r600_hw_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
src, subsrc, srcx, srcy, srcz, width, height);
}
void r600_init_blit_functions(struct r600_pipe_context *rctx)

4
src/gallium/drivers/r600/r600_buffer.c
View file

@ -124,7 +124,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
if ((transfer->box.x >= rbuffer->ranges[i].start) &&
(transfer->box.x < rbuffer->ranges[i].end))
flush = TRUE;
if (flush) {
r600_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
rbuffer->num_ranges = 0;
@ -180,7 +180,7 @@ static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
return;
}
}
rbuffer->ranges[rbuffer->num_ranges].start = offset;
rbuffer->ranges[rbuffer->num_ranges].end = offset+length;
rbuffer->num_ranges++;

4
src/gallium/drivers/r600/r600_pipe.c
View file

@ -186,7 +186,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
FREE(rctx);
return NULL;
}
rctx->vs_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
if (!rctx->vs_resource) {
FREE(rctx);
@ -406,7 +406,7 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED)) &&
r600_is_colorbuffer_format_supported(format)) {
r600_is_colorbuffer_format_supported(format)) {
retval |= usage &
(PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |

73
src/gallium/drivers/r600/r600_shader.c
View file

@ -444,7 +444,7 @@ static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
if (ctx->shader->input[input].centroid)
ij_index++;
}
/* work out gpr and base_chan from index */
gpr = ij_index / 2;
base_chan = (2 * (ij_index % 2)) + 1;
@ -477,9 +477,9 @@ static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
return r;
}
return 0;
}
}
static int tgsi_declaration(struct r600_shader_ctx *ctx)
{
struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
@ -549,7 +549,7 @@ static int r600_get_temp(struct r600_shader_ctx *ctx)
return ctx->temp_reg + ctx->max_driver_temp_used++;
}
/*
/*
* for evergreen we need to scan the shader to find the number of GPRs we need to
* reserve for interpolation.
*
@ -1001,7 +1001,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
if (r)
return r;
alu.inst = ctx->inst_info->r600_opcode;
if (!swap) {
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
@ -1046,7 +1046,7 @@ static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
return tgsi_op2_s(ctx, 1);
}
/*
/*
* r600 - trunc to -PI..PI range
* r700 - normalize by dividing by 2PI
* see fdo bug 27901
@ -1058,7 +1058,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
int r;
uint32_t lit_vals[4];
struct r600_bc_alu alu;
memset(lit_vals, 0, 4*4);
r = tgsi_split_constant(ctx, r600_src);
if (r)
@ -1084,7 +1084,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
alu.src[0] = r600_src[0];
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[1].chan = 0;
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
@ -1099,7 +1099,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
alu.dst.chan = 0;
alu.dst.sel = ctx->temp_reg;
alu.dst.write = 1;
@ -1129,7 +1129,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
alu.src[0].sel = ctx->temp_reg;
alu.src[0].chan = 0;
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[1].chan = 0;
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
@ -1908,10 +1908,10 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
r = r600_bc_add_alu(ctx->bc, &alu);
if (r)
return r;
/* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
* MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
* muladd has no writemask, have to use another temp
* muladd has no writemask, have to use another temp
*/
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
@ -1921,7 +1921,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
alu.src[0].chan = 0;
alu.src[1].sel = ctx->temp_reg;
alu.src[1].chan = 2;
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[2].chan = 0;
@ -1941,7 +1941,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
alu.src[0].chan = 1;
alu.src[1].sel = ctx->temp_reg;
alu.src[1].chan = 2;
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[2].chan = 0;
@ -1980,7 +1980,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
}
src_gpr = ctx->temp_reg;
}
opcode = ctx->inst_info->r600_opcode;
if (opcode == SQ_TEX_INST_SAMPLE &&
(inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
@ -2026,7 +2026,6 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
/* add shadow ambient support - gallium doesn't do it yet */
return 0;
}
static int tgsi_lrp(struct r600_shader_ctx *ctx)
@ -2156,7 +2155,7 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
r = r600_bc_add_alu(ctx->bc, &alu);
if (r)
return r;
}
}
if (use_temp)
return tgsi_helper_copy(ctx, inst);
return 0;
@ -2342,7 +2341,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
if (r)
return r;
}
/* result.y = tmp - floor(tmp); */
if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
@ -2627,7 +2626,7 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bc_alu alu;
int r;
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
@ -2663,18 +2662,18 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
int r;
memset(&alu, 0, sizeof(struct r600_bc_alu));
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_ARL:
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
break;
case TGSI_OPCODE_ARR:
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
break;
default:
assert(0);
return -1;
}
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_ARL:
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
break;
case TGSI_OPCODE_ARR:
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
break;
default:
assert(0);
return -1;
}
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
if (r)
@ -2703,8 +2702,8 @@ static int tgsi_opdst(struct r600_shader_ctx *ctx)
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
if (r)
return r;
if (i == 0 || i == 3) {
if (i == 0 || i == 3) {
alu.src[0].sel = V_SQ_ALU_SRC_1;
} else {
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
@ -2750,7 +2749,7 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
alu.src[1].sel = V_SQ_ALU_SRC_0;
alu.src[1].chan = 0;
alu.last = 1;
r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
@ -2804,7 +2803,7 @@ static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned r
ctx->bc->callstack[ctx->bc->call_sp].current + diff;
}
return;
}
}
switch (reason) {
case FC_PUSH_VPM:
ctx->bc->callstack[ctx->bc->call_sp].current++;
@ -2878,7 +2877,7 @@ static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_v
static void emit_testflag(struct r600_shader_ctx *ctx)
{
}
static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)

8
src/gallium/drivers/r600/r600_state.c
View file

@ -296,7 +296,7 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
unsigned eqRGB = state->rt[i].rgb_func;
unsigned srcRGB = state->rt[i].rgb_src_factor;
unsigned dstRGB = state->rt[i].rgb_dst_factor;
unsigned eqA = state->rt[i].alpha_func;
unsigned srcA = state->rt[i].alpha_src_factor;
unsigned dstA = state->rt[i].alpha_dst_factor;
@ -475,7 +475,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
0xFFFFFFFF, NULL);
@ -852,7 +852,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
color_info |= S_0280A0_SOURCE_FORMAT(1);
r600_pipe_state_add_reg(rstate,
@ -933,7 +933,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
util_copy_framebuffer_state(&rctx->framebuffer, state);
rctx->pframebuffer = &rctx->framebuffer;
/* build states */

11
src/gallium/drivers/r600/r600_state_common.c
View file

@ -202,10 +202,10 @@ void *r600_create_vertex_elements(struct pipe_context *ctx,
format = &v->hw_format[i];
switch (*format) {
FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
default:;
}
v->incompatible_layout =
@ -213,8 +213,7 @@ void *r600_create_vertex_elements(struct pipe_context *ctx,
v->elements[i].src_format != v->hw_format[i] ||
v->elements[i].src_offset % 4 != 0;
v->hw_format_size[i] =
align(util_format_get_blocksize(v->hw_format[i]), 4);
v->hw_format_size[i] = align(util_format_get_blocksize(v->hw_format[i]), 4);
}
return v;