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pan/mdg: Fix mask usage when filling before a spill

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Check the bytemask against 0xFFFF rather than 0xF so that the fill is
skipped for a .xyzw write rather than a .x write.

Set the mask on the store to 0xF when doing a read so that all
components are written back.

Fixes: 31d26ebf1b ("pan/mdg: Fill from TLS before spilling non-SSA nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
(cherry picked from commit c750ab8a38)
This commit is contained in:
Icecream95 2021-12-10 23:40:01 +13:00 • committed by Dylan Baker
parent cf289ff969
commit 7feaf6c548
2 changed files with 8 additions and 3 deletions
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2
.pick_status.json
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@ -679,7 +679,7 @@
"description": "pan/mdg: Fix mask usage when filling before a spill",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "31d26ebf1b9d0f819c894aec10c29a44052a995a"
},

9
src/panfrost/midgard/midgard_ra.c
View file

@ -946,10 +946,15 @@ mir_spill_register(
} else {
unsigned dest = spill_index++;
if (write_count > 1 && mir_bytemask(ins) != 0xF) {
unsigned bytemask = mir_bytemask(ins);
unsigned write_mask = mir_from_bytemask(mir_round_bytemask_up(
bytemask, 32), 32);
if (write_count > 1 && bytemask != 0xFFFF) {
midgard_instruction read =
v_load_store_scratch(dest, spill_slot, false, 0xF);
mir_insert_instruction_before_scheduled(ctx, block, ins, read);
write_mask = 0xF;
}
ins->dest = dest;
@ -977,7 +982,7 @@ mir_spill_register(
dest = spill_index++;
midgard_instruction st =
v_load_store_scratch(dest, spill_slot, true, ins->mask);
v_load_store_scratch(dest, spill_slot, true, write_mask);
mir_insert_instruction_after_scheduled(ctx, block, ins, st);
if (move) {