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radeonsi/sqtt: fix shader stage values

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shader_stages_mask and others expect MESA_SHADER_* based values,
not PIPE_SHADER_*...

Without this the fragment shader wouldn't appear in the "Pipelines"
pane of RGP.

Fixes: c276bde34a ("radeonsi/sqtt: export shader code to RGP")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13696>
(cherry picked from commit 3de072aaec)
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2021-11-05 22:00:33 +01:00 • committed by Eric Engestrom
parent 49a49fd20c
commit 7fd2714ddb
2 changed files with 16 additions and 15 deletions
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2
.pick_status.json
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@ -949,7 +949,7 @@
"description": "radeonsi/sqtt: fix shader stage values",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "c276bde34ae3c1ba823873d29774165664cdf129"
},

29
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -31,6 +31,7 @@
#include "ac_rgp.h"
#include "ac_sqtt.h"
#include "util/u_memory.h"
#include "tgsi/tgsi_from_mesa.h"
static void
si_emit_spi_config_cntl(struct si_context* sctx,
@ -959,7 +960,6 @@ si_sqtt_pipe_to_rgp_shader_stage(struct si_shader_key* key, enum pipe_shader_typ
}
}
static bool
si_sqtt_add_code_object(struct si_context* sctx,
uint64_t pipeline_hash,
@ -1004,20 +1004,21 @@ si_sqtt_add_code_object(struct si_context* sctx,
memcpy(code, shader->binary.uploaded_code, shader->binary.uploaded_code_size);
uint64_t va = shader->bo->gpu_address;
record->shader_data[i].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size);
record->shader_data[i].hash[1] = record->shader_data[i].hash[0];
record->shader_data[i].code_size = shader->binary.uploaded_code_size;
record->shader_data[i].code = code;
record->shader_data[i].vgpr_count = shader->config.num_vgprs;
record->shader_data[i].sgpr_count = shader->config.num_sgprs;
record->shader_data[i].base_address = va & 0xffffffffffff;
record->shader_data[i].elf_symbol_offset = 0;
record->shader_data[i].hw_stage = hw_stage;
record->shader_data[i].is_combined = false;
record->shader_data[i].scratch_memory_size = shader->config.scratch_bytes_per_wave;
record->shader_data[i].wavefront_size = si_get_shader_wave_size(shader);
unsigned gl_shader_stage = tgsi_processor_to_shader_stage(i);
record->shader_data[gl_shader_stage].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size);
record->shader_data[gl_shader_stage].hash[1] = record->shader_data[gl_shader_stage].hash[0];
record->shader_data[gl_shader_stage].code_size = shader->binary.uploaded_code_size;
record->shader_data[gl_shader_stage].code = code;
record->shader_data[gl_shader_stage].vgpr_count = shader->config.num_vgprs;
record->shader_data[gl_shader_stage].sgpr_count = shader->config.num_sgprs;
record->shader_data[gl_shader_stage].base_address = va & 0xffffffffffff;
record->shader_data[gl_shader_stage].elf_symbol_offset = 0;
record->shader_data[gl_shader_stage].hw_stage = hw_stage;
record->shader_data[gl_shader_stage].is_combined = false;
record->shader_data[gl_shader_stage].scratch_memory_size = shader->config.scratch_bytes_per_wave;
record->shader_data[gl_shader_stage].wavefront_size = si_get_shader_wave_size(shader);
record->shader_stages_mask |= (1 << i);
record->shader_stages_mask |= 1 << gl_shader_stage;
record->num_shaders_combined++;
}