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synced 2026-01-13 05:30:16 +01:00
iris: more depth stuffs...
still missing stencil
This commit is contained in:
parent
02890c75b5
commit
7fb7704b2e
2 changed files with 77 additions and 12 deletions
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@ -85,6 +85,7 @@ struct blorp_params;
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#define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
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#define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
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#define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
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#define IRIS_DIRTY_DEPTH_BUFFER (1ull << 40)
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enum brw_param_domain {
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BRW_PARAM_DOMAIN_BUILTIN = 0,
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@ -270,6 +271,7 @@ struct iris_context {
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struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
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struct pipe_stencil_ref stencil_ref;
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struct pipe_framebuffer_state framebuffer;
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struct iris_depth_buffer_state *cso_depthbuffer;
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struct pipe_resource *sampler_table_resource[MESA_SHADER_STAGES];
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uint32_t sampler_table_offset[MESA_SHADER_STAGES];
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@ -1250,11 +1250,12 @@ iris_set_viewport_states(struct pipe_context *ctx,
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ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
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}
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struct iris_depth_state
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struct iris_depth_buffer_state
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{
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uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
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uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
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uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
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uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
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GENX(3DSTATE_STENCIL_BUFFER_length) +
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GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
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GENX(3DSTATE_CLEAR_PARAMS_length)];
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};
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static void
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@ -1262,6 +1263,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
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const struct pipe_framebuffer_state *state)
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{
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struct iris_context *ice = (struct iris_context *) ctx;
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struct iris_screen *screen = (struct iris_screen *)ctx->screen;
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struct isl_device *isl_dev = &screen->isl_dev;
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struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
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if (cso->samples != state->samples) {
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@ -1287,11 +1290,63 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
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pipe_surface_reference(&cso->zsbuf, state->zsbuf);
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//struct isl_depth_stencil_hiz_emit_info info = {
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//.mocs = MOCS_WB,
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//};
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struct iris_depth_buffer_state *cso_z =
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malloc(sizeof(struct iris_depth_buffer_state));
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// XXX: depth buffers
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struct isl_view view = {
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/* Some nice defaults */
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.base_level = 0,
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.levels = 1,
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.base_array_layer = 0,
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.array_len = 1,
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.swizzle = ISL_SWIZZLE_IDENTITY,
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};
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struct isl_depth_stencil_hiz_emit_info info = {
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.view = &view,
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.mocs = MOCS_WB,
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};
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struct iris_resource *zres =
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(void *) (cso->zsbuf ? cso->zsbuf->texture : NULL);
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if (zres) {
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view.usage |= ISL_SURF_USAGE_DEPTH_BIT;
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info.depth_surf = &zres->surf;
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info.depth_address = zres->bo->gtt_offset;
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view.format = zres->surf.format;
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view.base_level = cso->zsbuf->u.tex.level;
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view.base_array_layer = cso->zsbuf->u.tex.first_layer;
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view.array_len =
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cso->zsbuf->u.tex.last_layer - cso->zsbuf->u.tex.first_layer + 1;
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info.hiz_usage = ISL_AUX_USAGE_NONE;
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}
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#if 0
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if (stencil_mt) {
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view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
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info.stencil_surf = &stencil_mt->surf;
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if (!depth_mt) {
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view.base_level = stencil_irb->mt_level - stencil_irb->mt->first_level;
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view.base_array_layer = stencil_irb->mt_layer;
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view.array_len = MAX2(stencil_irb->layer_count, 1);
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view.format = stencil_mt->surf.format;
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}
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uint32_t stencil_offset = 0;
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info.stencil_address = stencil_mt->bo->gtt_offset + stencil_mt->offset;
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}
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#endif
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isl_emit_depth_stencil_hiz_s(isl_dev, cso_z->packets, &info);
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ice->state.cso_depthbuffer = cso_z;
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ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
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}
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static void
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@ -2353,10 +2408,18 @@ iris_upload_render_state(struct iris_context *ice,
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}
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}
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// XXX: 3DSTATE_DEPTH_BUFFER
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// XXX: 3DSTATE_HIER_DEPTH_BUFFER
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// XXX: 3DSTATE_STENCIL_BUFFER
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// XXX: 3DSTATE_CLEAR_PARAMS
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if (dirty & IRIS_DIRTY_DEPTH_BUFFER) {
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struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
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struct iris_depth_buffer_state *cso_z = ice->state.cso_depthbuffer;
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iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));
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if (cso_fb->zsbuf) {
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struct iris_resource *zres = (void *) cso_fb->zsbuf->texture;
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// XXX: depth might not be writable...
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iris_use_pinned_bo(batch, zres->bo, true);
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}
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}
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if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
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iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
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