fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 21:50:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris/compute: Split out iris_load_indirect_location

Browse source 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
This commit is contained in:
Jordan Justen 2019-02-13 11:10:39 -08:00 • committed by Marge Bot
parent 6557c8294d
commit 7f48c6b6a2
1 changed files with 29 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

49
src/gallium/drivers/iris/iris_state.c
View file

@ -6570,6 +6570,33 @@ iris_upload_render_state(struct iris_context *ice,
iris_batch_sync_region_end(batch);
}
static void
iris_load_indirect_location(struct iris_context *ice,
struct iris_batch *batch,
const struct pipe_grid_info *grid)
{
#define GPGPU_DISPATCHDIMX 0x2500
#define GPGPU_DISPATCHDIMY 0x2504
#define GPGPU_DISPATCHDIMZ 0x2508
assert(grid->indirect);
struct iris_state_ref *grid_size = &ice->state.grid_size;
struct iris_bo *bo = iris_resource_bo(grid_size->res);
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMX;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMY;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMZ;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8);
}
}
static void
iris_upload_gpgpu_walker(struct iris_context *ice,
struct iris_batch *batch,
@ -6679,26 +6706,8 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
}
}
#define GPGPU_DISPATCHDIMX 0x2500
#define GPGPU_DISPATCHDIMY 0x2504
#define GPGPU_DISPATCHDIMZ 0x2508
if (grid->indirect) {
struct iris_state_ref *grid_size = &ice->state.grid_size;
struct iris_bo *bo = iris_resource_bo(grid_size->res);
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMX;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMY;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMZ;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8);
}
}
if (grid->indirect)
iris_load_indirect_location(ice, batch, grid);
const uint32_t right_mask = brw_cs_right_mask(group_size, simd_size);