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nir: Add upper bound for AMD shader arg intrinsics.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>
This commit is contained in:
Timur Kristóf 2022-03-23 18:44:57 +01:00 • committed by Marge Bot
parent 2755acbdad
commit 7f189e3467
2 changed files with 12 additions and 2 deletions
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7
src/compiler/nir/nir_intrinsics.py
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@ -234,6 +234,9 @@ index("uint8_t", "offset1")
# in hardware, instead of 4). # in hardware, instead of 4).
index("bool", "st64") index("bool", "st64")
# When set, range analysis will use it for nir_unsigned_upper_bound
index("unsigned", "arg_upper_bound_u32_amd")
# Separate source/dest access flags for copies # Separate source/dest access flags for copies
index("enum gl_access_qualifier", "dst_access") index("enum gl_access_qualifier", "dst_access")
index("enum gl_access_qualifier", "src_access") index("enum gl_access_qualifier", "src_access")
@ -1346,8 +1349,8 @@ system_value("intersection_opaque_amd", 1, bit_sizes=[1])
# Load forced VRS rates. # Load forced VRS rates.
intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER])
intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
# src[] = { 64-bit base address, 32-bit offset }. # src[] = { 64-bit base address, 32-bit offset }.
intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32],

7
src/compiler/nir/nir_range_analysis.c
View file

@ -1416,6 +1416,13 @@ nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht,
/* Very generous maximum: TCS/TES executed by largest possible workgroup */ /* Very generous maximum: TCS/TES executed by largest possible workgroup */
res = config->max_workgroup_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u); res = config->max_workgroup_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u);
break; break;
case nir_intrinsic_load_scalar_arg_amd:
case nir_intrinsic_load_vector_arg_amd: {
uint32_t upper_bound = nir_intrinsic_arg_upper_bound_u32_amd(intrin);
if (upper_bound)
res = upper_bound;
break;
}
default: default:
break; break;
} }