diff --git a/.pick_status.json b/.pick_status.json
index ed21bdccfc9..e97131ae56c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -754,7 +754,7 @@
         "description": "anv: disable CCS for Source2 games on Xe2",
         "nominated": true,
         "nomination_type": 4,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index e988569c9a6..aada27472ed 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -80,6 +80,7 @@ static const driOptionDescription anv_dri_options[] = {
       DRI_CONF_VK_XWAYLAND_WAIT_READY(false)
       DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0)
       DRI_CONF_ANV_DISABLE_FCV(false)
+      DRI_CONF_ANV_DISABLE_XE2_CCS(false)
       DRI_CONF_ANV_EXTERNAL_MEMORY_IMPLICIT_SYNC(true)
       DRI_CONF_ANV_FORCE_GUC_LOW_LATENCY(false)
       DRI_CONF_ANV_SAMPLE_MASK_OUT_OPENGL_BEHAVIOUR(false)
@@ -2418,6 +2419,9 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
       goto fail_fd;
    }
 
+   if (devinfo.ver == 20 && instance->disable_xe2_ccs)
+      intel_debug |= DEBUG_NO_CCS;
+
    /* Disable Wa_16013994831 on Gfx12.0 because we found other cases where we
     * need to always disable preemption :
     *    - https://gitlab.freedesktop.org/mesa/mesa/-/issues/5963
@@ -2758,6 +2762,8 @@ anv_init_dri_options(struct anv_instance *instance)
     instance->enable_tbimr = driQueryOptionb(&instance->dri_options, "intel_tbimr");
     instance->disable_fcv =
             driQueryOptionb(&instance->dri_options, "anv_disable_fcv");
+    instance->disable_xe2_ccs =
+            driQueryOptionb(&instance->dri_options, "anv_disable_xe2_ccs");
     instance->external_memory_implicit_sync =
             driQueryOptionb(&instance->dri_options, "anv_external_memory_implicit_sync");
     instance->compression_control_enabled =
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index a1788d11d59..66873879fca 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1274,6 +1274,7 @@ struct anv_instance {
     unsigned                                    force_vk_vendor;
     bool                                        has_fake_sparse;
     bool                                        disable_fcv;
+    bool                                        disable_xe2_ccs;
     bool                                        compression_control_enabled;
     bool                                        anv_fake_nonlocal_memory;
 
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 033b4cd89dc..b9e2e17996e 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -1251,6 +1251,12 @@ TODO: document the other workarounds.
         <application name="Total War: WARHAMMER III" executable="TotalWarhammer3">
             <option name="anv_fake_nonlocal_memory" value="true" />
         </application>
+        <!-- Source2 games seem confused by the CCS-only memory type, so
+             temporarily disable CCS. More details on the issue:
+             https://gitlab.freedesktop.org/mesa/mesa/-/issues/11520 -->
+        <engine engine_name_match="Source2">
+            <option name="anv_disable_xe2_ccs" value="true" />
+        </engine>
         <!--
         Disable 16-bit feature on zink and angle so that GLES mediump doesn't
         lower to our inefficent 16-bit shader support.  No need to do so for
diff --git a/src/util/driconf.h b/src/util/driconf.h
index 70f82e82dbb..464e0713a0f 100644
--- a/src/util/driconf.h
+++ b/src/util/driconf.h
@@ -784,6 +784,10 @@
    DRI_CONF_OPT_B(anv_disable_fcv, def, \
                   "Disable FCV optimization")
 
+#define DRI_CONF_ANV_DISABLE_XE2_CCS(def) \
+   DRI_CONF_OPT_B(anv_disable_xe2_ccs, def, \
+                  "Disable CCS optimization on Xe2")
+
 #define DRI_CONF_ANV_EXTERNAL_MEMORY_IMPLICIT_SYNC(def) \
    DRI_CONF_OPT_B(anv_external_memory_implicit_sync, def, "Implicit sync on external BOs")