fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 22:10:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/fs: Allow spilling of non-contiguous registers.

Browse source 
This should be working fine now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94997
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez 2016-04-27 02:07:08 -07:00
parent 6fc5dd5b6a
commit 7eb4966887
1 changed files with 2 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View file

@ -835,30 +835,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF) {
if (inst->src[i].file == VGRF)
spill_costs[inst->src[i].nr] += loop_scale;
/* Register spilling logic assumes full-width registers; smeared
* registers have a width of 1 so if we try to spill them we'll
* generate invalid assembly. This shouldn't be a problem because
* smeared registers are only used as short-term temporaries when
* loading pull constants, so spilling them is unlikely to reduce
* register pressure anyhow.
*/
if (!inst->src[i].is_contiguous()) {
no_spill[inst->src[i].nr] = true;
}
}
}
if (inst->dst.file == VGRF) {
if (inst->dst.file == VGRF)
spill_costs[inst->dst.nr] += inst->regs_written * loop_scale;
if (!inst->dst.is_contiguous()) {
no_spill[inst->dst.nr] = true;
}
}
switch (inst->opcode) {
case BRW_OPCODE_DO: