From 7eabc5d6fc08b0be9949289ba4e0227f3d33b74e Mon Sep 17 00:00:00 2001 From: Vitaliy Triang3l Kuzmin Date: Fri, 2 Jun 2023 22:58:47 +0300 Subject: [PATCH] radv: Enable POPS collision wave ID shader argument MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Signed-off-by: Vitaliy Triang3l Kuzmin Part-of: --- src/amd/vulkan/radv_pipeline_graphics.c | 3 +++ src/amd/vulkan/radv_shader.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 63e68f4f0b7..2eb1b7a63ae 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -3321,6 +3321,9 @@ radv_emit_fragment_shader(const struct radv_device *device, struct radeon_cmdbuf radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil, ps->info.ps.writes_sample_mask, ps->info.ps.writes_mrt0_alpha)); + + if (pdevice->rad_info.gfx_level >= GFX9 && pdevice->rad_info.gfx_level < GFX11) + radeon_set_context_reg(ctx_cs, R_028C40_PA_SC_SHADER_CONTROL, S_028C40_LOAD_COLLISION_WAVEID(ps->info.ps.pops)); } static void diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index e66e2ad8caa..0fe496d1fa1 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1499,7 +1499,8 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi case MESA_SHADER_FRAGMENT: config->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B028_LOAD_PROVOKING_VTX(info->ps.load_provoking_vtx); - config->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B02C_EXCP_EN(excp_en); + config->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B02C_EXCP_EN(excp_en) | + S_00B02C_LOAD_COLLISION_WAVEID(info->ps.pops && pdevice->rad_info.gfx_level < GFX11); break; case MESA_SHADER_GEOMETRY: config->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10);