From 7eab94d5420b4c7fae17a7348e4e4f10da675550 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Tue, 5 May 2026 12:52:46 -0700 Subject: [PATCH] intel/nir: fix sparse shadow comparison for BRW While Jay overwrites sparse_tex->op with the newer opcodes that only return red and the sparse stuff, BRW keeps using the original opcode of the cloned instruction, so it can't change def->num_components. This was not previously detectable since we did not have sparse enabled for depth/stencil on Anv for a while. A patch to re-enable that was proposed a while ago (MR !37423), never merged, but then a recent attempt to try to merge it (by me) detected this regression. Let's fix the regression first, then we can finally re-enable sparse depth/stencil support in Anv, hopefully. Fixes: 7468261d3d13 ("intel/nir: Make intel_nir_lower_sparse work for either brw or jay") Reviewed-by: Kenneth Graunke Signed-off-by: Paulo Zanoni Part-of: --- src/intel/compiler/intel_nir_lower_sparse.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/intel_nir_lower_sparse.c b/src/intel/compiler/intel_nir_lower_sparse.c index 8a52fb93ed7..ead2f5403c7 100644 --- a/src/intel/compiler/intel_nir_lower_sparse.c +++ b/src/intel/compiler/intel_nir_lower_sparse.c @@ -136,13 +136,15 @@ split_tex_residency(nir_builder *b, nir_tex_instr *tex, bool jay) /* Clone the original instruction */ nir_tex_instr *sparse_tex = nir_instr_as_tex(nir_instr_clone(b->shader, &tex->instr)); - nir_def_init(&sparse_tex->instr, &sparse_tex->def, 2, tex->def.bit_size); + nir_def_init(&sparse_tex->instr, &sparse_tex->def, + tex->def.num_components, tex->def.bit_size); nir_builder_instr_insert(b, &sparse_tex->instr); if (jay) { sparse_tex->op = tex->op == nir_texop_txf ? nir_texop_sparse_residency_txf_intel : nir_texop_sparse_residency_intel; + sparse_tex->def.num_components = 2; } /* txl/txb/tex and tg4 both access the same pixels for residency checking