diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index d6bfc64fe84..257dfd12011 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -207,12 +207,14 @@ static brw_reg
 emit_work_group_id_setup(nir_to_brw_state &ntb)
 {
    fs_visitor &s = ntb.s;
-   const fs_builder &bld = ntb.bld;
+   const fs_builder &bld = ntb.bld.scalar_group();
 
    assert(gl_shader_stage_is_compute(s.stage));
 
    brw_reg id = bld.vgrf(BRW_TYPE_UD, 3);
 
+   id.is_scalar = true;
+
    struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_TYPE_UD));
    bld.MOV(id, r0_1);
 
@@ -1947,6 +1949,10 @@ get_nir_def(nir_to_brw_state &ntb, const nir_def &def)
          nir_instr_as_intrinsic(def.parent_instr);
 
       switch (instr->intrinsic) {
+      case nir_intrinsic_load_workgroup_id:
+         is_scalar = true;
+         break;
+
       case nir_intrinsic_load_uniform:
          is_scalar = get_nir_src(ntb, instr->src[0]).is_scalar;
          break;
@@ -4598,10 +4604,14 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
 
    case nir_intrinsic_load_workgroup_id: {
       brw_reg val = ntb.system_values[SYSTEM_VALUE_WORKGROUP_ID];
+      const fs_builder ubld = bld.scalar_group();
+
       assert(val.file != BAD_FILE);
+      assert(val.is_scalar);
+
       dest.type = val.type;
       for (unsigned i = 0; i < 3; i++)
-         bld.MOV(offset(dest, bld, i), offset(val, bld, i));
+         ubld.MOV(offset(dest, ubld, i), offset(val, ubld, i));
       break;
    }