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panfrost/perf: Add Gx25 perfcounters
This commit is contained in:
Boris Brezillon
Christoph Pillmayer
parent
825ac92605
commit
7e7d9cddc7
3 changed files with 318 additions and 2 deletions
316
src/panfrost/perf/Gx25.xml
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316
src/panfrost/perf/Gx25.xml
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<!--
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Copyright © 2025 Collabora, Ltd.
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SPDX-License-Identifier: MIT
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-->
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<metrics id="TKRx" arch_major="13">
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<category name="CSF" per_cpu="no">
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<event offset="4" advanced="yes" counter="GPU_ACTIVE" title="GPU_ACTIVE" name="GPU_ACTIVE" description="Number of cycles the GPU was active" units="cycles"/>
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<event offset="5" advanced="yes" counter="MCU_ACTIVE" title="MCU_ACTIVE" name="MCU_ACTIVE" description="Number of cycles the MCU has been active" units="cycles"/>
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<event offset="6" advanced="yes" counter="GPU_ITER_ACTIVE" title="GPU_ITER_ACTIVE" name="GPU_ITER_ACTIVE" description="Number of cycles any iterator was active" units="cycles"/>
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<event offset="7" advanced="yes" counter="MMU_FLUSH_COUNT" title="MMU_FLUSH_COUNT" name="MMU_FLUSH_COUNT" description="Number of MMU flush requests" units="requests"/>
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<event offset="8" advanced="yes" counter="MESSAGES_SENT" title="MESSAGES_SENT" name="MESSAGES_SENT" description="Number of job control bus messages sent" units="jobs"/>
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<event offset="9" advanced="yes" counter="MESSAGES_RECEIVED" title="MESSAGES_RECEIVED" name="MESSAGES_RECEIVED" description="Number of job control bus messages received" units="jobs"/>
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<event offset="10" advanced="yes" counter="GPU_IRQ_ACTIVE" title="GPU_IRQ_ACTIVE" name="GPU_IRQ_ACTIVE" description="Number of cycles with active interrupts" units="cycles"/>
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<event offset="11" advanced="yes" counter="GPU_IRQ_COUNT" title="GPU_IRQ_COUNT" name="GPU_IRQ_COUNT" description="Number of interrupts the GPU raised" units="interrupts"/>
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<event offset="12" advanced="yes" counter="CACHE_FLUSH_CYCLES" title="CACHE_FLUSH_CYCLES" name="CACHE_FLUSH_CYCLES" description="Number of cycles a L2C cache flush was active" units="cycles"/>
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<event offset="13" advanced="yes" counter="CACHE_FLUSH" title="CACHE_FLUSH" name="CACHE_FLUSH" description="Number of L2 cache flushes" units="requests"/>
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<event offset="14" advanced="yes" counter="DOORBELL_IRQ_ACTIVE" title="DOORBELL_IRQ_ACTIVE" name="DOORBELL_IRQ_ACTIVE" description="Number of cycles the doorbell interrupt has been asserted" units="cycles"/>
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<event offset="15" advanced="yes" counter="DOORBELL_IRQ_COUNT" title="DOORBELL_IRQ_COUNT" name="DOORBELL_IRQ_COUNT" description="Number of times the doorbell interrupt has been raised" units="interrupts"/>
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<event offset="16" advanced="yes" counter="CEU_ACTIVE" title="CEU_ACTIVE" name="CEU_ACTIVE" description="Number of cycles the CEU has been active" units="cycles"/>
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<event offset="17" advanced="yes" counter="CEU_READY_BLOCKED" title="CEU_READY_BLOCKED" name="CEU_READY_BLOCKED" description="Number of cycles the CEU has been stalled because it is waiting for a requested command or commands" units="cycles"/>
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<event offset="18" advanced="yes" counter="CEU_COMMAND_COUNT" title="CEU_COMMAND_COUNT" name="CEU_COMMAND_COUNT" description="Number of native commands that the CEU has executed" units="requests"/>
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<event offset="19" advanced="yes" counter="CEU_STATE_TRANSFER_STALLED" title="CEU_STATE_TRANSFER_STALLED" name="CEU_STATE_TRANSFER_STALLED" description="Number of cycles the CEU was stalled during state transfer" units="cycles"/>
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<event offset="20" advanced="yes" counter="CEU_LSU_REQUEST_STALLED" title="CEU_LSU_REQUEST_STALLED" name="CEU_LSU_REQUEST_STALLED" description="Number of stalled cycles because there are no free LSU handlers" units="cycles"/>
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<event offset="21" advanced="yes" counter="LSU_ACTIVE" title="LSU_ACTIVE" name="LSU_ACTIVE" description="Number of cycles the LSU was active" units="cycles"/>
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<event offset="22" advanced="yes" counter="LSU_OPERATIONS_COMPLETED" title="LSU_OPERATIONS_COMPLETED" name="LSU_OPERATIONS_COMPLETED" description="Number of LSU operations that have completed" units="requests"/>
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<event offset="23" advanced="yes" counter="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" title="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" name="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" description="Total number of cycles LSU handlers have been active" units="cycles"/>
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<event offset="32" advanced="yes" counter="ITER_COMP_ACTIVE" title="ITER_COMP_ACTIVE" name="ITER_COMP_ACTIVE" description="Number of cycles the compute iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
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<event offset="33" advanced="yes" counter="ITER_COMP_JOB_COMPLETED" title="ITER_COMP_JOB_COMPLETED" name="ITER_COMP_JOB_COMPLETED" description="Number of jobs the compute iterator has completed" units="jobs"/>
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<event offset="34" advanced="yes" counter="ITER_COMP_TASK_COMPLETED" title="ITER_COMP_TASK_COMPLETED" name="ITER_COMP_TASK_COMPLETED" description="Number of tasks the compute iterator has completed" units="tasks"/>
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<event offset="35" advanced="yes" counter="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" title="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" name="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" description="Total number of cycles compute endpoints have been processing compute tasks" units="cycles"/>
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<event offset="36" advanced="yes" counter="ITER_COMP_IRQ_ACTIVE" title="ITER_COMP_IRQ_ACTIVE" name="ITER_COMP_IRQ_ACTIVE" description="Number of cycles the compute iterator interrupt has been asserted" units="cycles"/>
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<event offset="37" advanced="yes" counter="ITER_COMP_IRQ_COUNT" title="ITER_COMP_IRQ_COUNT" name="ITER_COMP_IRQ_COUNT" description="Number of times the compute iterator interrupt has gone active" units="interrupts"/>
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<event offset="38" advanced="yes" counter="ITER_COMP_READY_BLOCKED" title="ITER_COMP_READY_BLOCKED" name="ITER_COMP_READY_BLOCKED" description="Number of cycles the compute iterator has had at least one task but no ready endpoints" units="cycles"/>
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<event offset="39" advanced="yes" counter="ITER_COMP_EP_DRAIN" title="ITER_COMP_EP_DRAIN" name="ITER_COMP_EP_DRAIN" description="Number of cycles the compute iterator is waiting for IDVS work to drain" units="cycles"/>
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<event offset="48" advanced="yes" counter="ITER_FRAG_ACTIVE" title="ITER_FRAG_ACTIVE" name="ITER_FRAG_ACTIVE" description="Number of cycles the fragment iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
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<event offset="49" advanced="yes" counter="ITER_FRAG_JOB_COMPLETED" title="ITER_FRAG_JOB_COMPLETED" name="ITER_FRAG_JOB_COMPLETED" description="Number of jobs the fragment iterator has completed" units="jobs"/>
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<event offset="50" advanced="yes" counter="ITER_FRAG_TASK_COMPLETED" title="ITER_FRAG_TASK_COMPLETED" name="ITER_FRAG_TASK_COMPLETED" description="Number of tasks the fragment iterator has completed" units="tasks"/>
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<event offset="51" advanced="yes" counter="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" title="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" name="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" description="Total number of cycles fragment endpoints have been processing fragment tasks" units="cycles"/>
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<event offset="52" advanced="yes" counter="ITER_FRAG_IRQ_ACTIVE" title="ITER_FRAG_IRQ_ACTIVE" name="ITER_FRAG_IRQ_ACTIVE" description="Number of cycles the fragment iterator interrupt has been asserted" units="cycles"/>
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<event offset="53" advanced="yes" counter="ITER_FRAG_IRQ_COUNT" title="ITER_FRAG_IRQ_COUNT" name="ITER_FRAG_IRQ_COUNT" description="Number of times the fragment iterator interrupt has gone active" units="interrupts"/>
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<event offset="54" advanced="yes" counter="ITER_FRAG_READY_BLOCKED" title="ITER_FRAG_READY_BLOCKED" name="ITER_FRAG_READY_BLOCKED" description="Number of cycles the fragment iterator has had at least one task but no ready endpoints" units="cycles"/>
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<event offset="55" advanced="yes" counter="ITER_FRAG_TILE_MAP_READ_WAIT" title="ITER_FRAG_TILE_MAP_READ_WAIT" name="ITER_FRAG_TILE_MAP_READ_WAIT" description="Number of cycles the fragment iterator was waiting on a read of the tile enable mask" units="cycles"/>
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<event offset="64" advanced="yes" counter="ITER_TILER_ACTIVE" title="ITER_TILER_ACTIVE" name="ITER_TILER_ACTIVE" description="Number of cycles the tile iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
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<event offset="65" advanced="yes" counter="ITER_TILER_JOB_COMPLETED" title="ITER_TILER_JOB_COMPLETED" name="ITER_TILER_JOB_COMPLETED" description="Number of jobs the tile iterator has completed" units="jobs"/>
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<event offset="66" advanced="yes" counter="ITER_TILER_IDVS_TASK_COMPLETED" title="ITER_TILER_IDVS_TASK_COMPLETED" name="ITER_TILER_IDVS_TASK_COMPLETED" description="Number of IDVS tasks the compute endpoints have completed" units="tasks"/>
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<event offset="67" advanced="yes" counter="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" title="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" name="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" description="Total number of cycles compute endpoints have been processing IDVS tasks" units="cycles"/>
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<event offset="68" advanced="yes" counter="ITER_TILER_IRQ_ACTIVE" title="ITER_TILER_IRQ_ACTIVE" name="ITER_TILER_IRQ_ACTIVE" description="Number of cycles the tile iterator interrupt has been asserted" units="cycles"/>
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<event offset="69" advanced="yes" counter="ITER_TILER_IRQ_COUNT" title="ITER_TILER_IRQ_COUNT" name="ITER_TILER_IRQ_COUNT" description="Number of times the tiler iterator interrupt has gone active" units="interrupts"/>
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<event offset="70" advanced="yes" counter="ITER_TILER_READY_BLOCKED" title="ITER_TILER_READY_BLOCKED" name="ITER_TILER_READY_BLOCKED" description="Number of cycles the tile iterator has had at least one task but no ready endpoints" units="cycles"/>
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<event offset="71" advanced="yes" counter="ITER_TILER_EP_DRAIN" title="ITER_TILER_EP_DRAIN" name="ITER_TILER_EP_DRAIN" description="Number of cycles of spent draining compute work before a tiler task can be issued" units="cycles"/>
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<event offset="80" advanced="yes" counter="CSHWIF0_ENABLED" title="CSHWIF0_ENABLED" name="CSHWIF0_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="81" advanced="yes" counter="CSHWIF0_PREFETCH_MISS_COUNT" title="CSHWIF0_PREFETCH_MISS_COUNT" name="CSHWIF0_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="82" advanced="yes" counter="CSHWIF0_IRQ_ACTIVE" title="CSHWIF0_IRQ_ACTIVE" name="CSHWIF0_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="83" advanced="yes" counter="CSHWIF0_IRQ_COUNT" title="CSHWIF0_IRQ_COUNT" name="CSHWIF0_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="84" advanced="yes" counter="CSHWIF0_WAIT_BLOCKED" title="CSHWIF0_WAIT_BLOCKED" name="CSHWIF0_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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<event offset="86" advanced="yes" counter="CSHWIF1_ENABLED" title="CSHWIF1_ENABLED" name="CSHWIF1_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="87" advanced="yes" counter="CSHWIF1_PREFETCH_MISS_COUNT" title="CSHWIF1_PREFETCH_MISS_COUNT" name="CSHWIF1_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="88" advanced="yes" counter="CSHWIF1_IRQ_ACTIVE" title="CSHWIF1_IRQ_ACTIVE" name="CSHWIF1_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="89" advanced="yes" counter="CSHWIF1_IRQ_COUNT" title="CSHWIF1_IRQ_COUNT" name="CSHWIF1_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="90" advanced="yes" counter="CSHWIF1_WAIT_BLOCKED" title="CSHWIF1_WAIT_BLOCKED" name="CSHWIF1_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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<event offset="92" advanced="yes" counter="CSHWIF2_ENABLED" title="CSHWIF2_ENABLED" name="CSHWIF2_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="93" advanced="yes" counter="CSHWIF2_PREFETCH_MISS_COUNT" title="CSHWIF2_PREFETCH_MISS_COUNT" name="CSHWIF2_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="94" advanced="yes" counter="CSHWIF2_IRQ_ACTIVE" title="CSHWIF2_IRQ_ACTIVE" name="CSHWIF2_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="95" advanced="yes" counter="CSHWIF2_IRQ_COUNT" title="CSHWIF2_IRQ_COUNT" name="CSHWIF2_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="96" advanced="yes" counter="CSHWIF2_WAIT_BLOCKED" title="CSHWIF2_WAIT_BLOCKED" name="CSHWIF2_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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<event offset="98" advanced="yes" counter="CSHWIF3_ENABLED" title="CSHWIF3_ENABLED" name="CSHWIF3_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="99" advanced="yes" counter="CSHWIF3_PREFETCH_MISS_COUNT" title="CSHWIF3_PREFETCH_MISS_COUNT" name="CSHWIF3_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="100" advanced="yes" counter="CSHWIF3_IRQ_ACTIVE" title="CSHWIF3_IRQ_ACTIVE" name="CSHWIF3_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="101" advanced="yes" counter="CSHWIF3_IRQ_COUNT" title="CSHWIF3_IRQ_COUNT" name="CSHWIF3_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="102" advanced="yes" counter="CSHWIF3_WAIT_BLOCKED" title="CSHWIF3_WAIT_BLOCKED" name="CSHWIF3_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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<event offset="104" advanced="yes" counter="CSHWIF4_ENABLED" title="CSHWIF4_ENABLED" name="CSHWIF4_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="105" advanced="yes" counter="CSHWIF4_PREFETCH_MISS_COUNT" title="CSHWIF4_PREFETCH_MISS_COUNT" name="CSHWIF4_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="106" advanced="yes" counter="CSHWIF4_IRQ_ACTIVE" title="CSHWIF4_IRQ_ACTIVE" name="CSHWIF4_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="107" advanced="yes" counter="CSHWIF4_IRQ_COUNT" title="CSHWIF4_IRQ_COUNT" name="CSHWIF4_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="108" advanced="yes" counter="CSHWIF4_WAIT_BLOCKED" title="CSHWIF4_WAIT_BLOCKED" name="CSHWIF4_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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<event offset="110" advanced="yes" counter="CSHWIF5_ENABLED" title="CSHWIF5_ENABLED" name="CSHWIF5_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
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<event offset="111" advanced="yes" counter="CSHWIF5_PREFETCH_MISS_COUNT" title="CSHWIF5_PREFETCH_MISS_COUNT" name="CSHWIF5_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
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<event offset="112" advanced="yes" counter="CSHWIF5_IRQ_ACTIVE" title="CSHWIF5_IRQ_ACTIVE" name="CSHWIF5_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
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<event offset="113" advanced="yes" counter="CSHWIF5_IRQ_COUNT" title="CSHWIF5_IRQ_COUNT" name="CSHWIF5_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
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<event offset="114" advanced="yes" counter="CSHWIF5_WAIT_BLOCKED" title="CSHWIF5_WAIT_BLOCKED" name="CSHWIF5_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
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</category>
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<category name="Tiler" per_cpu="no">
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<event offset="4" advanced="yes" counter="TILER_ACTIVE" title="TILER_ACTIVE" name="TILER_ACTIVE" description="Number of cycles the tiler is active" units="cycles"/>
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<event offset="5" advanced="yes" counter="JOBS_PROCESSED" title="JOBS_PROCESSED" name="JOBS_PROCESSED" description="Number of processed tiler jobs" units="jobs"/>
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<event offset="6" advanced="yes" counter="TRIANGLES" title="TRIANGLES" name="TRIANGLES" description="Number of Triangles processed" units="requests"/>
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<event offset="7" advanced="yes" counter="LINES" title="LINES" name="LINES" description="Number of Lines processed" units="requests"/>
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<event offset="8" advanced="yes" counter="POINTS" title="POINTS" name="POINTS" description="Number of Points processed" units="requests"/>
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<event offset="9" advanced="yes" counter="FRONT_FACING" title="FRONT_FACING" name="FRONT_FACING" description="Number of front facing primitives" units="requests"/>
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<event offset="10" advanced="yes" counter="BACK_FACING" title="BACK_FACING" name="BACK_FACING" description="Number of back facing primitives" units="requests"/>
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<event offset="11" advanced="yes" counter="PRIM_VISIBLE" title="PRIM_VISIBLE" name="PRIM_VISIBLE" description="Number of visible primitives" units="requests"/>
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<event offset="12" advanced="yes" counter="PRIM_FACE_CULLED" title="PRIM_FACE_CULLED" name="PRIM_FACE_CULLED" description="Number of primitives culled by facing" units="requests"/>
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<event offset="13" advanced="yes" counter="PRIM_FRUSTUM_CULLED" title="PRIM_FRUSTUM_CULLED" name="PRIM_FRUSTUM_CULLED" description="Number of primitives culled as being outside the view frustum" units="requests"/>
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<event offset="14" advanced="yes" counter="PRIM_SAMPLE_CULLED" title="PRIM_SAMPLE_CULLED" name="PRIM_SAMPLE_CULLED" description="Number of primitives culled because they cannot produce samples" units="requests"/>
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<event offset="15" advanced="yes" counter="BIN_ALLOC_INIT" title="BIN_ALLOC_INIT" name="BIN_ALLOC_INIT" description="Number of initial bin allocations" units="requests"/>
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<event offset="16" advanced="yes" counter="BIN_ALLOC_OVERFLOW" title="BIN_ALLOC_OVERFLOW" name="BIN_ALLOC_OVERFLOW" description="Number of overflow bin allocations" units="requests"/>
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<event offset="17" advanced="yes" counter="BUS_READ" title="BUS_READ" name="BUS_READ" description="Number of read data beats (512-bit) from the L2 cache" units="beats"/>
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<event offset="18" advanced="yes" counter="BUS_WRITE_UTLB0" title="BUS_WRITE_UTLB0" name="BUS_WRITE_UTLB0" description="Number of write data beats (512-bit) to the L2 cache through µTLB #0" units="beats"/>
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<event offset="19" advanced="yes" counter="BUS_WRITE_UTLB1" title="BUS_WRITE_UTLB1" name="BUS_WRITE_UTLB1" description="Number of write data beats (512-bit) to the L2 cache through µTLB #1" units="beats"/>
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<event offset="20" advanced="yes" counter="SUSPENDED" title="SUSPENDED" name="SUSPENDED" description="Number of times the tiler has been suspended" units="requests"/>
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<event offset="21" advanced="yes" counter="POS_SHADER_WARPS" title="POS_SHADER_WARPS" name="POS_SHADER_WARPS" description="Number of position shading warps" units="warps"/>
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<event offset="22" advanced="yes" counter="POS_SHADER_PARTIAL_WARPS" title="POS_SHADER_PARTIAL_WARPS" name="POS_SHADER_PARTIAL_WARPS" description="Number of position shading warps that were only partially filled" units="warps"/>
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<event offset="23" advanced="yes" counter="POS_SHADER_STALL" title="POS_SHADER_STALL" name="POS_SHADER_STALL" description="Number of cycles stalled on shading request interface requesting position shading" units="cycles"/>
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<event offset="24" advanced="yes" counter="POS_FIFO_FULL" title="POS_FIFO_FULL" name="POS_FIFO_FULL" description="Number of cycles the position FIFO is full and blocking position shading requests" units="cycles"/>
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<event offset="25" advanced="yes" counter="PREFETCH_STALL" title="PREFETCH_STALL" name="PREFETCH_STALL" description="Number of cycles the prefetcher has valid data but is stalled by the latency FIFO" units="cycles"/>
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<event offset="26" advanced="yes" counter="VCACHE_HIT" title="VCACHE_HIT" name="VCACHE_HIT" description="Number of vertex cache hits" units="requests"/>
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<event offset="27" advanced="yes" counter="LPA_HIT" title="LPA_HIT" name="LPA_HIT" description="Number of hits in late primitive assembly buffer" units="requests"/>
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<event offset="30" advanced="yes" counter="VFETCH_VERTEX_WAIT" title="VFETCH_VERTEX_WAIT" name="VFETCH_VERTEX_WAIT" description="Number of cycles waiting for a valid shaded positions to be loaded" units="cycles"/>
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<event offset="32" advanced="yes" counter="PRIMASSY_STALL" title="PRIMASSY_STALL" name="PRIMASSY_STALL" description="Number of cycles the primitive assembly output is stalled" units="cycles"/>
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<event offset="33" advanced="yes" counter="RESUMED" title="RESUMED" name="RESUMED" description="Number of times the tiler has been resumed" units="requests"/>
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<event offset="34" advanced="yes" counter="VBU_HIT" title="VBU_HIT" name="VBU_HIT" description="Number of vertex bitmap unit hits" units="requests"/>
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<event offset="36" advanced="yes" counter="VAR_SHADER_WARPS" title="VAR_SHADER_WARPS" name="VAR_SHADER_WARPS" description="Number of varying shading warps" units="warps"/>
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<event offset="37" advanced="yes" counter="VAR_SHADER_PARTIAL_WARPS" title="VAR_SHADER_PARTIAL_WARPS" name="VAR_SHADER_PARTIAL_WARPS" description="Number of varying shading warps that were only partially filled" units="warps"/>
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<event offset="38" advanced="yes" counter="VAR_SHADER_STALL" title="VAR_SHADER_STALL" name="VAR_SHADER_STALL" description="Number of cycles stalled on shading request interface requesting varying shading" units="cycles"/>
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<event offset="39" advanced="yes" counter="BINNER_STALL" title="BINNER_STALL" name="BINNER_STALL" description="Number of cycles the binner output is stalled" units="cycles"/>
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<event offset="40" advanced="yes" counter="ITER_STALL" title="ITER_STALL" name="ITER_STALL" description="Number of cycles the iterator output is stalled" units="cycles"/>
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<event offset="41" advanced="yes" counter="COMPRESS_MISS" title="COMPRESS_MISS" name="COMPRESS_MISS" description="Number of misses in the write compressor" units="requests"/>
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<event offset="42" advanced="yes" counter="ASN_R_STALL" title="ASN_R_STALL" name="ASN_R_STALL" description="Number of cycles the ASN R transactions are stalled" units="cycles"/>
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<event offset="43" advanced="yes" counter="PCACHE_HIT" title="PCACHE_HIT" name="PCACHE_HIT" description="Number of pointer cache hits" units="requests"/>
|
||||
<event offset="44" advanced="yes" counter="PCACHE_MISS" title="PCACHE_MISS" name="PCACHE_MISS" description="Number of Pointer Cache misses" units="requests"/>
|
||||
<event offset="45" advanced="yes" counter="PCACHE_MISS_STALL" title="PCACHE_MISS_STALL" name="PCACHE_MISS_STALL" description="Number of cycles waiting to process a miss in the pointer cache" units="cycles"/>
|
||||
<event offset="46" advanced="yes" counter="PCACHE_EVICT_STALL" title="PCACHE_EVICT_STALL" name="PCACHE_EVICT_STALL" description="Number of cycles waiting for eviction in the pointer cache to complete" units="cycles"/>
|
||||
<event offset="47" advanced="yes" counter="PMGR_PTR_WR_STALL" title="PMGR_PTR_WR_STALL" name="PMGR_PTR_WR_STALL" description="Number of cycles waiting for write-back pointer in the pointer manager" units="cycles"/>
|
||||
<event offset="48" advanced="yes" counter="PMGR_PTR_RD_STALL" title="PMGR_PTR_RD_STALL" name="PMGR_PTR_RD_STALL" description="Number of cycles waiting for a valid pointer in the pointer manager" units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="PMGR_CMD_WR_STALL" title="PMGR_CMD_WR_STALL" name="PMGR_CMD_WR_STALL" description="Number of cycles waiting for the write buffer to accept" units="cycles"/>
|
||||
<event offset="50" advanced="yes" counter="WRBUF_ACTIVE" title="WRBUF_ACTIVE" name="WRBUF_ACTIVE" description="Number of cycles the write buffer is active" units="cycles"/>
|
||||
<event offset="51" advanced="yes" counter="WRBUF_HIT" title="WRBUF_HIT" name="WRBUF_HIT" description="Number of write buffer hits" units="requests"/>
|
||||
<event offset="52" advanced="yes" counter="WRBUF_MISS" title="WRBUF_MISS" name="WRBUF_MISS" description="Number of Write Buffer misses" units="requests"/>
|
||||
<event offset="53" advanced="yes" counter="WRBUF_NO_FREE_LINE_STALL" title="WRBUF_NO_FREE_LINE_STALL" name="WRBUF_NO_FREE_LINE_STALL" description="Number of cycles stalled waiting for a free line in the write buffer" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_ASN_ID_STALL" title="WRBUF_NO_ASN_ID_STALL" name="WRBUF_NO_ASN_ID_STALL" description="Number of cycles the ASN interface is stalled due to the max transaction limit" units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_ASN_STALL" title="WRBUF_ASN_STALL" name="WRBUF_ASN_STALL" description="Number of cycles the ASN write data interface is stalled" units="cycles"/>
|
||||
<event offset="56" advanced="yes" counter="UTLB0_TRANS" title="UTLB0_TRANS" name="UTLB0_TRANS" description="Number of transactions processed" units="transactions"/>
|
||||
<event offset="57" advanced="yes" counter="UTLB0_TRANS_HIT" title="UTLB0_TRANS_HIT" name="UTLB0_TRANS_HIT" description="Number of micro-TLB hits" units="requests"/>
|
||||
<event offset="58" advanced="yes" counter="UTLB0_TRANS_STALL" title="UTLB0_TRANS_STALL" name="UTLB0_TRANS_STALL" description="Number of cycles transactions are stalled on the input" units="cycles"/>
|
||||
<event offset="59" advanced="yes" counter="UTLB0_MMU_REQ" title="UTLB0_MMU_REQ" name="UTLB0_MMU_REQ" description="Number of requests sent to the MMU" units="requests"/>
|
||||
<event offset="60" advanced="yes" counter="UTLB1_TRANS" title="UTLB1_TRANS" name="UTLB1_TRANS" description="Number of transactions processed" units="transactions"/>
|
||||
<event offset="61" advanced="yes" counter="UTLB1_TRANS_HIT" title="UTLB1_TRANS_HIT" name="UTLB1_TRANS_HIT" description="Number of micro-TLB hits" units="requests"/>
|
||||
<event offset="62" advanced="yes" counter="UTLB1_TRANS_STALL" title="UTLB1_TRANS_STALL" name="UTLB1_TRANS_STALL" description="Number of cycles transactions are stalled on the input" units="cycles"/>
|
||||
<event offset="63" advanced="yes" counter="UTLB1_MMU_REQ" title="UTLB1_MMU_REQ" name="UTLB1_MMU_REQ" description="Number of requests sent to the MMU" units="requests"/>
|
||||
<event offset="64" advanced="yes" counter="PRIMASSY_POS_SHADER_WAIT" title="PRIMASSY_POS_SHADER_WAIT" name="PRIMASSY_POS_SHADER_WAIT" description="Number of cycles late primitive assembly is waiting for position shading" units="cycles"/>
|
||||
<event offset="65" advanced="yes" counter="RUN_COMMANDS" title="RUN_COMMANDS" name="RUN_COMMANDS" description="Number of RUN commands processed by the tiler" units="requests"/>
|
||||
<event offset="66" advanced="yes" counter="FINISH_COMMANDS" title="FINISH_COMMANDS" name="FINISH_COMMANDS" description="Number of FINISH_TILING commands processed by the tiler" units="requests"/>
|
||||
<event offset="67" advanced="yes" counter="SUSPENDED_EMPTY" title="SUSPENDED_EMPTY" name="SUSPENDED_EMPTY" description="Number of times the tiler has been suspended with no unprocessed jobs" units="jobs"/>
|
||||
<event offset="68" advanced="yes" counter="OOM_COUNT" title="OOM_COUNT" name="OOM_COUNT" description="Number of times an out-of-memory event is raised" units="requests"/>
|
||||
<event offset="69" advanced="yes" counter="OOM_STALL" title="OOM_STALL" name="OOM_STALL" description="Number of cycles between an out-of-memory event and new memory is provided" units="cycles"/>
|
||||
<event offset="70" advanced="yes" counter="PRIM_SCISSOR_CULLED" title="PRIM_SCISSOR_CULLED" name="PRIM_SCISSOR_CULLED" description="Number of primitives culled as being outside the scissor box" units="requests"/>
|
||||
<event offset="71" advanced="yes" counter="PRIM_VISIBLE_DVS" title="PRIM_VISIBLE_DVS" name="PRIM_VISIBLE_DVS" description="Number of primitives selected for deferred vertex shading" units="requests"/>
|
||||
<event offset="72" advanced="yes" counter="FUSED_PRIMITIVES" title="FUSED_PRIMITIVES" name="FUSED_PRIMITIVES" description="Number of fused primitives" units="requests"/>
|
||||
<event offset="73" advanced="yes" counter="FUSED_PRIMITIVES_VISIBLE" title="FUSED_PRIMITIVES_VISIBLE" name="FUSED_PRIMITIVES_VISIBLE" description="Number of visible fused primitives" units="requests"/>
|
||||
<event offset="74" advanced="yes" counter="HEAP_CHUNKS_USED" title="HEAP_CHUNKS_USED" name="HEAP_CHUNKS_USED" description="Number of heap chunks used by the tiler" units="requests"/>
|
||||
<event offset="75" advanced="yes" counter="JOBS_EMPTY" title="JOBS_EMPTY" name="JOBS_EMPTY" description="Number of tiler jobs that are skipped as empty" units="jobs"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="FRAG_ACTIVE" title="FRAG_ACTIVE" name="FRAG_ACTIVE" description="Number of cycles fragment processing is active" units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="EXEC_INSTR_NARROW" title="EXEC_INSTR_NARROW" name="EXEC_INSTR_NARROW" description="Number of narrow arithmetic operations" units="requests"/>
|
||||
<event offset="6" advanced="yes" counter="FRAG_PRIM_RAST" title="FRAG_PRIM_RAST" name="FRAG_PRIM_RAST" description="Number of rasterized primitives" units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="FRAG_FPK_ACTIVE" title="FRAG_FPK_ACTIVE" name="FRAG_FPK_ACTIVE" description="Number of cycles the forward pixel kill queue contains data" units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="FRAG_STARVING" title="FRAG_STARVING" name="FRAG_STARVING" description="Number of cycles the fragment front end is starving the execution engine of new threads" units="cycles"/>
|
||||
<event offset="9" advanced="yes" counter="FRAG_WARPS" title="FRAG_WARPS" name="FRAG_WARPS" description="Number of fragment warps started" units="warps"/>
|
||||
<event offset="10" advanced="yes" counter="FRAG_PARTIAL_QUADS_RAST" title="FRAG_PARTIAL_QUADS_RAST" name="FRAG_PARTIAL_QUADS_RAST" description="Number of partial fragment quads rasterized" units="quads"/>
|
||||
<event offset="11" advanced="yes" counter="FRAG_QUADS_RAST" title="FRAG_QUADS_RAST" name="FRAG_QUADS_RAST" description="Number of quads rasterized" units="quads"/>
|
||||
<event offset="12" advanced="yes" counter="FRAG_QUADS_EZS_TEST" title="FRAG_QUADS_EZS_TEST" name="FRAG_QUADS_EZS_TEST" description="Number of quads doing early ZS test" units="quads"/>
|
||||
<event offset="13" advanced="yes" counter="FRAG_QUADS_EZS_UPDATE" title="FRAG_QUADS_EZS_UPDATE" name="FRAG_QUADS_EZS_UPDATE" description="Number of quads doing early ZS update" units="quads"/>
|
||||
<event offset="14" advanced="yes" counter="FRAG_QUADS_EZS_KILL" title="FRAG_QUADS_EZS_KILL" name="FRAG_QUADS_EZS_KILL" description="Number of quads killed by the early ZS test" units="quads"/>
|
||||
<event offset="15" advanced="yes" counter="FRAG_LZS_TEST" title="FRAG_LZS_TEST" name="FRAG_LZS_TEST" description="Number of quads doing late ZS test" units="quads"/>
|
||||
<event offset="16" advanced="yes" counter="FRAG_LZS_KILL" title="FRAG_LZS_KILL" name="FRAG_LZS_KILL" description="Number of quads killed by the late ZS test" units="quads"/>
|
||||
<event offset="17" advanced="yes" counter="WARP_REG_SIZE_64" title="WARP_REG_SIZE_64" name="WARP_REG_SIZE_64" description="Number of warps created with 64 registers allocated" units="warps"/>
|
||||
<event offset="18" advanced="yes" counter="FRAG_PTILES" title="FRAG_PTILES" name="FRAG_PTILES" description="Number of physical tiles rendered" units="tiles"/>
|
||||
<event offset="19" advanced="yes" counter="FRAG_TRANS_ELIM" title="FRAG_TRANS_ELIM" name="FRAG_TRANS_ELIM" description="Number of transaction elimination signature matches" units="transactions"/>
|
||||
<event offset="20" advanced="yes" counter="QUAD_FPK_KILLER" title="QUAD_FPK_KILLER" name="QUAD_FPK_KILLER" description="Number of quads which enter the FPK queue and can kill other quads" units="quads"/>
|
||||
<event offset="21" advanced="yes" counter="FULL_QUAD_WARPS" title="FULL_QUAD_WARPS" name="FULL_QUAD_WARPS" description="Number of warps created with all quads active" units="warps"/>
|
||||
<event offset="22" advanced="yes" counter="COMPUTE_ACTIVE" title="COMPUTE_ACTIVE" name="COMPUTE_ACTIVE" description="Number of cycles compute processing is active" units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="COMPUTE_TASKS" name="COMPUTE_TASKS" description="Number of compute tasks" units="tasks"/>
|
||||
<event offset="24" advanced="yes" counter="COMPUTE_WARPS" title="COMPUTE_WARPS" name="COMPUTE_WARPS" description="Number of compute warps started" units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="COMPUTE_STARVING" name="COMPUTE_STARVING" description="Number of cycles unable to issue new compute threads" units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="EXEC_CORE_ACTIVE" title="EXEC_CORE_ACTIVE" name="EXEC_CORE_ACTIVE" description="Number of cycles the execution core is active" units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_INSTR_FMA" title="EXEC_INSTR_FMA" name="EXEC_INSTR_FMA" description="Number of FMA arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="EXEC_INSTR_CVT" title="EXEC_INSTR_CVT" name="EXEC_INSTR_CVT" description="Number of CVT arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="29" advanced="yes" counter="EXEC_INSTR_SFU" title="EXEC_INSTR_SFU" name="EXEC_INSTR_SFU" description="Number of SFU arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_MSG" title="EXEC_INSTR_MSG" name="EXEC_INSTR_MSG" description="Number of message instruction per Processing Unit" units="instructions"/>
|
||||
<event offset="31" advanced="yes" counter="EXEC_INSTR_DIVERGED" title="EXEC_INSTR_DIVERGED" name="EXEC_INSTR_DIVERGED" description="Number of diverged instructions per Processing Unit" units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="EXEC_ICACHE_MISS" name="EXEC_ICACHE_MISS" description="Number of I-cache capacity misses" units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="EXEC_STARVE_ARITH" name="EXEC_STARVE_ARITH" description="Processing Unit starvation" units="requests"/>
|
||||
<event offset="34" advanced="yes" counter="CALL_BLEND_SHADER" title="CALL_BLEND_SHADER" name="CALL_BLEND_SHADER" description="Number of calls to blend shaders per Processing Unit" units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="TEX_MSGI_NUM_FLITS" title="TEX_MSGI_NUM_FLITS" name="TEX_MSGI_NUM_FLITS" description="Number of texturing request message flits received by the texture mapper" units="requests"/>
|
||||
<event offset="36" advanced="yes" counter="TEX_DFCH_CLK_STALLED" title="TEX_DFCH_CLK_STALLED" name="TEX_DFCH_CLK_STALLED" description="Number of cycles a quad is stalled waiting for a descriptor fetch" units="cycles"/>
|
||||
<event offset="37" advanced="yes" counter="TEX_TFCH_CLK_STALLED" title="TEX_TFCH_CLK_STALLED" name="TEX_TFCH_CLK_STALLED" description="Number of cycles a quad is stalled waiting to enter the texel fetcher" units="cycles"/>
|
||||
<event offset="38" advanced="yes" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="TEX_TFCH_STARVED_PENDING_DATA_FETCH" name="TEX_TFCH_STARVED_PENDING_DATA_FETCH" description="Number of cycles the parking buffer was not empty, but no filtering operation was issued" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="TEX_FILT_NUM_OPERATIONS" title="TEX_FILT_NUM_OPERATIONS" name="TEX_FILT_NUM_OPERATIONS" description="Number of operations executed in the filtering unit" units="requests"/>
|
||||
<event offset="42" advanced="yes" counter="TEX_MSGO_NUM_MSG" title="TEX_MSGO_NUM_MSG" name="TEX_MSGO_NUM_MSG" description="Number of response messages sent" units="requests"/>
|
||||
<event offset="43" advanced="yes" counter="TEX_RSPS_NUM_OPERATIONS" title="TEX_RSPS_NUM_OPERATIONS" name="TEX_RSPS_NUM_OPERATIONS" description="Number of cycles the texture mapper outputs data" units="cycles"/>
|
||||
<event offset="44" advanced="yes" counter="LS_MEM_READ_FULL" title="LS_MEM_READ_FULL" name="LS_MEM_READ_FULL" description="Number of memory read accesses, full cache line" units="requests"/>
|
||||
<event offset="45" advanced="yes" counter="LS_MEM_READ_SHORT" title="LS_MEM_READ_SHORT" name="LS_MEM_READ_SHORT" description="Number of memory read accesses, partial cache line" units="requests"/>
|
||||
<event offset="46" advanced="yes" counter="LS_MEM_WRITE_FULL" title="LS_MEM_WRITE_FULL" name="LS_MEM_WRITE_FULL" description="Number of memory write accesses, full cache line" units="requests"/>
|
||||
<event offset="47" advanced="yes" counter="LS_MEM_WRITE_SHORT" title="LS_MEM_WRITE_SHORT" name="LS_MEM_WRITE_SHORT" description="Number of memory write accesses, partial cache line" units="requests"/>
|
||||
<event offset="48" advanced="yes" counter="LS_MEM_ATOMIC" title="LS_MEM_ATOMIC" name="LS_MEM_ATOMIC" description="Number of atomic memory accesses" units="requests"/>
|
||||
<event offset="49" advanced="yes" counter="VARY_INSTR" title="VARY_INSTR" name="VARY_INSTR" description="Number of varying instructions" units="instructions"/>
|
||||
<event offset="50" advanced="yes" counter="VARY_SLOT_32" title="VARY_SLOT_32" name="VARY_SLOT_32" description="Number of 32-bit varying slots" units="requests"/>
|
||||
<event offset="51" advanced="yes" counter="VARY_SLOT_16" title="VARY_SLOT_16" name="VARY_SLOT_16" description="Number of 16-bit varying slots" units="requests"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="ATTR_INSTR" name="ATTR_INSTR" description="Number of load/store attribute calculations completed" units="requests"/>
|
||||
<event offset="53" advanced="yes" counter="SHADER_CORE_ACTIVE" title="SHADER_CORE_ACTIVE" name="SHADER_CORE_ACTIVE" description="Number of cycles a shader core is active" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="BEATS_RD_FTC" title="BEATS_RD_FTC" name="BEATS_RD_FTC" description="Number of read beats for the fragment thread creator" units="beats"/>
|
||||
<event offset="55" advanced="yes" counter="BEATS_RD_FTC_EXT" title="BEATS_RD_FTC_EXT" name="BEATS_RD_FTC_EXT" description="Number of external read beats for the fragment thread creator" units="beats"/>
|
||||
<event offset="56" advanced="yes" counter="BEATS_RD_LSC" title="BEATS_RD_LSC" name="BEATS_RD_LSC" description="Number of read beats for the load/store cache" units="beats"/>
|
||||
<event offset="57" advanced="yes" counter="BEATS_RD_LSC_EXT" title="BEATS_RD_LSC_EXT" name="BEATS_RD_LSC_EXT" description="Number of external read beats for the load/store cache" units="beats"/>
|
||||
<event offset="58" advanced="yes" counter="BEATS_RD_TEX" title="BEATS_RD_TEX" name="BEATS_RD_TEX" description="Number of read beats for the texture cache" units="beats"/>
|
||||
<event offset="59" advanced="yes" counter="BEATS_RD_TEX_EXT" title="BEATS_RD_TEX_EXT" name="BEATS_RD_TEX_EXT" description="Number of external read beats for the texture cache" units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="BEATS_RD_OTHER" name="BEATS_RD_OTHER" description="Number of read beats for all other requesters" units="beats"/>
|
||||
<event offset="61" advanced="yes" counter="BEATS_WR_LSC_OTHER" title="BEATS_WR_LSC_OTHER" name="BEATS_WR_LSC_OTHER" description="Number of write beats from the load/store cache due to other reasons" units="beats"/>
|
||||
<event offset="62" advanced="yes" counter="BEATS_WR_TIB" title="BEATS_WR_TIB" name="BEATS_WR_TIB" description="Number of write beats for the tile buffers" units="beats"/>
|
||||
<event offset="63" advanced="yes" counter="BEATS_WR_LSC_WB" title="BEATS_WR_LSC_WB" name="BEATS_WR_LSC_WB" description="Number of write beats from the load/store cache due to write-backs" units="beats"/>
|
||||
<event offset="68" advanced="yes" counter="FRAG_QUADS_COARSE" title="FRAG_QUADS_COARSE" name="FRAG_QUADS_COARSE" description="Number of coarse quads before early culling" units="quads"/>
|
||||
<event offset="69" advanced="yes" counter="FRAG_SHADER_THREADS" title="FRAG_SHADER_THREADS" name="FRAG_SHADER_THREADS" description="Number of fragment shader threads executed" units="threads"/>
|
||||
<event offset="70" advanced="yes" counter="RT_RAY_TRI" title="RT_RAY_TRI" name="RT_RAY_TRI" description="Number of triangle batches tested" units="requests"/>
|
||||
<event offset="71" advanced="yes" counter="RT_RAY_BOX" title="RT_RAY_BOX" name="RT_RAY_BOX" description="Number of acceleration structure nodes tested" units="requests"/>
|
||||
<event offset="72" advanced="yes" counter="RT_RAY_TRI_BIN_1_4" title="RT_RAY_TRI_BIN_1_4" name="RT_RAY_TRI_BIN_1_4" description="Number of triangle batches tested with 1 to 4 active rays in the warp" units="warps"/>
|
||||
<event offset="73" advanced="yes" counter="RT_RAY_TRI_BIN_5_8" title="RT_RAY_TRI_BIN_5_8" name="RT_RAY_TRI_BIN_5_8" description="Number of triangle batches tested with 5 to 8 active rays in the warp" units="warps"/>
|
||||
<event offset="74" advanced="yes" counter="RT_RAY_TRI_BIN_9_12" title="RT_RAY_TRI_BIN_9_12" name="RT_RAY_TRI_BIN_9_12" description="Number of triangle batches tested with 9 to 12 active rays in the warp" units="warps"/>
|
||||
<event offset="75" advanced="yes" counter="RT_RAY_TRI_BIN_13_16" title="RT_RAY_TRI_BIN_13_16" name="RT_RAY_TRI_BIN_13_16" description="Number of triangle batches tested with 13 to 16 active rays in the warp" units="warps"/>
|
||||
<event offset="76" advanced="yes" counter="RT_RAY_BOX_BIN_1_4" title="RT_RAY_BOX_BIN_1_4" name="RT_RAY_BOX_BIN_1_4" description="Number of acceleration structure nodes visited with 1 to 4 active rays in the warp" units="warps"/>
|
||||
<event offset="77" advanced="yes" counter="RT_RAY_BOX_BIN_5_8" title="RT_RAY_BOX_BIN_5_8" name="RT_RAY_BOX_BIN_5_8" description="Number of acceleration structure nodes visited with 5 to 8 active rays in the warp" units="warps"/>
|
||||
<event offset="78" advanced="yes" counter="RT_RAY_BOX_BIN_9_12" title="RT_RAY_BOX_BIN_9_12" name="RT_RAY_BOX_BIN_9_12" description="Number of acceleration structure nodes visited with 9 to 12 active rays in the warp" units="warps"/>
|
||||
<event offset="79" advanced="yes" counter="RT_RAY_BOX_BIN_13_16" title="RT_RAY_BOX_BIN_13_16" name="RT_RAY_BOX_BIN_13_16" description="Number of acceleration structure nodes visited with 13 to 16 active rays in the warp" units="warps"/>
|
||||
<event offset="80" advanced="yes" counter="RT_OPAQUE_HIT" title="RT_OPAQUE_HIT" name="RT_OPAQUE_HIT" description="Number of opaque triangles hit" units="requests"/>
|
||||
<event offset="81" advanced="yes" counter="RT_NON_OPAQUE_HIT" title="RT_NON_OPAQUE_HIT" name="RT_NON_OPAQUE_HIT" description="Number of non-opaque triangles hit" units="requests"/>
|
||||
<event offset="82" advanced="yes" counter="RT_TERM_FIRST_HIT" title="RT_TERM_FIRST_HIT" name="RT_TERM_FIRST_HIT" description="Number of rays that terminate on their first hit" units="requests"/>
|
||||
<event offset="83" advanced="yes" counter="RT_MISS" title="RT_MISS" name="RT_MISS" description="Number of ray-triangle intersection tests that resulted in a miss" units="requests"/>
|
||||
<event offset="84" advanced="yes" counter="RT_RAYS_STARTED" title="RT_RAYS_STARTED" name="RT_RAYS_STARTED" description="Number of rays that tested the root node of a top level acceleration structure" units="requests"/>
|
||||
<event offset="85" advanced="yes" counter="RT_RAY_BOX_ISSUED" title="RT_RAY_BOX_ISSUED" name="RT_RAY_BOX_ISSUED" description="Number of active issue cycles for the ray box data path" units="cycles"/>
|
||||
<event offset="86" advanced="yes" counter="RT_RAY_TRI_ISSUED" title="RT_RAY_TRI_ISSUED" name="RT_RAY_TRI_ISSUED" description="Number of active issue cycles for the ray triangle data path" units="cycles"/>
|
||||
<event offset="87" advanced="yes" counter="TEX_CFCH_NUM_OUTPUT_OPERATIONS" title="TEX_CFCH_NUM_OUTPUT_OPERATIONS" name="TEX_CFCH_NUM_OUTPUT_OPERATIONS" description="Number of cycles the texture mapper spends on transferring uncompressed texel data" units="cycles"/>
|
||||
<event offset="88" advanced="yes" counter="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" title="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" name="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" description="Number of cycles processing simple texture formats" units="cycles"/>
|
||||
<event offset="89" advanced="yes" counter="TEX_CFCH_NUM_L1_CL_OPERATIONS" title="TEX_CFCH_NUM_L1_CL_OPERATIONS" name="TEX_CFCH_NUM_L1_CL_OPERATIONS" description="Number of cycles the texture L1 cache outputs data" units="cycles"/>
|
||||
<event offset="90" advanced="yes" counter="TEX_CFCH_NUM_L1_CT_OPERATIONS" title="TEX_CFCH_NUM_L1_CT_OPERATIONS" name="TEX_CFCH_NUM_L1_CT_OPERATIONS" description="Number of cycles the texture L1 cache is being accessed" units="cycles"/>
|
||||
<event offset="91" advanced="yes" counter="TEX_MSGO_NUM_SINGLE_QUAD_MSG" title="TEX_MSGO_NUM_SINGLE_QUAD_MSG" name="TEX_MSGO_NUM_SINGLE_QUAD_MSG" description="Number of return messages containing only one quad" units="quads"/>
|
||||
<event offset="92" advanced="yes" counter="TEX_TFCH_NUM_TCL_OPERATIONS" title="TEX_TFCH_NUM_TCL_OPERATIONS" name="TEX_TFCH_NUM_TCL_OPERATIONS" description="Number of cycles the texture mapper spends on reading data from the texture cache" units="cycles"/>
|
||||
<event offset="93" advanced="yes" counter="TEX_CFCH_NUM_RP_OPERATIONS" title="TEX_CFCH_NUM_RP_OPERATIONS" name="TEX_CFCH_NUM_RP_OPERATIONS" description="Number of cycles processing complex texture formats" units="cycles"/>
|
||||
<event offset="94" advanced="yes" counter="TEX_TIDX_NUM_OPERATIONS" title="TEX_TIDX_NUM_OPERATIONS" name="TEX_TIDX_NUM_OPERATIONS" description="Number of cycles the texture mapper spends on calculating texel indices" units="cycles"/>
|
||||
<event offset="95" advanced="yes" counter="TEX_MSGI_CLK_STARVED" title="TEX_MSGI_CLK_STARVED" name="TEX_MSGI_CLK_STARVED" description="Number of cycles the texture pipe is active and the message input unit is idle waiting to receive a message" units="cycles"/>
|
||||
<event offset="96" advanced="yes" counter="TEX_TEXP_CLK_ACTIVE" title="TEX_TEXP_CLK_ACTIVE" name="TEX_TEXP_CLK_ACTIVE" description="Number of clock cycles that the texture pipe has been active" units="cycles"/>
|
||||
<event offset="97" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="FRAG_PRIMITIVES_OUT" name="FRAG_PRIMITIVES_OUT" description="Number of primitives" units="requests"/>
|
||||
<event offset="98" advanced="yes" counter="FRAG_PRIMITIVES_HSR_CULLED" title="FRAG_PRIMITIVES_HSR_CULLED" name="FRAG_PRIMITIVES_HSR_CULLED" description="Number of primitives filtered by the Primitive Classification Unit" units="requests"/>
|
||||
<event offset="99" advanced="yes" counter="FRAG_PRIMITIVES_OUT_PRE_PASS" title="FRAG_PRIMITIVES_OUT_PRE_PASS" name="FRAG_PRIMITIVES_OUT_PRE_PASS" description="Number of primitives rendered in the fragment prepass" units="requests"/>
|
||||
<event offset="100" advanced="yes" counter="FRAG_PRIMITIVES_HSR_DISABLED" title="FRAG_PRIMITIVES_HSR_DISABLED" name="FRAG_PRIMITIVES_HSR_DISABLED" description="Number of primitives in the main-pass that cannot be culled by HSR ID testing" units="requests"/>
|
||||
<event offset="101" advanced="yes" counter="FRAG_QUADS_HSR_BUF_EZS_UPDATE" title="FRAG_QUADS_HSR_BUF_EZS_UPDATE" name="FRAG_QUADS_HSR_BUF_EZS_UPDATE" description="Number of quads updating the HSR ID buffer during early ZS testing" units="quads"/>
|
||||
<event offset="102" advanced="yes" counter="FRAG_QUADS_HSR_BUF_TEST" title="FRAG_QUADS_HSR_BUF_TEST" name="FRAG_QUADS_HSR_BUF_TEST" description="Number of quads tested against the HSR ID buffer" units="quads"/>
|
||||
<event offset="103" advanced="yes" counter="FRAG_QUADS_HSR_BUF_KILLED" title="FRAG_QUADS_HSR_BUF_KILLED" name="FRAG_QUADS_HSR_BUF_KILLED" description="Number of quads killed against the HSR ID buffer" units="quads"/>
|
||||
<event offset="104" advanced="yes" counter="FRAG_WARPS_PRE_PASS" title="FRAG_WARPS_PRE_PASS" name="FRAG_WARPS_PRE_PASS" description="Number of warps created in the fragment prepass" units="warps"/>
|
||||
<event offset="105" advanced="yes" counter="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" title="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" name="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" description="Number of cycles a Fragment Main-pass was stalled by a fragment prepass" units="cycles"/>
|
||||
<event offset="106" advanced="yes" counter="DVS_WARPS" title="DVS_WARPS" name="DVS_WARPS" description="Number of DVS shading warps" units="warps"/>
|
||||
<event offset="112" advanced="yes" counter="EXEC_MSG_STALLED_TEX" title="EXEC_MSG_STALLED_TEX" name="EXEC_MSG_STALLED_TEX" description="Cycles stalled trying to send a message to TEX unit" units="cycles"/>
|
||||
<event offset="113" advanced="yes" counter="EXEC_MSG_STALLED_VARY" title="EXEC_MSG_STALLED_VARY" name="EXEC_MSG_STALLED_VARY" description="Cycles stalled trying to send a message to VARY unit" units="cycles"/>
|
||||
<event offset="114" advanced="yes" counter="EXEC_MSG_STALLED_BLEND" title="EXEC_MSG_STALLED_BLEND" name="EXEC_MSG_STALLED_BLEND" description="Cycles stalled trying to send a message to BLEND unit" units="cycles"/>
|
||||
<event offset="115" advanced="yes" counter="EXEC_MSG_STALLED_ZS" title="EXEC_MSG_STALLED_ZS" name="EXEC_MSG_STALLED_ZS" description="Cycles stalled trying to send a message to ZS unit" units="cycles"/>
|
||||
<event offset="116" advanced="yes" counter="EXEC_MSG_STALLED_LSC" title="EXEC_MSG_STALLED_LSC" name="EXEC_MSG_STALLED_LSC" description="Cycles stalled trying to send a message to LSC unit" units="cycles"/>
|
||||
<event offset="117" advanced="yes" counter="EXEC_MSG_STALLED_ATTR" title="EXEC_MSG_STALLED_ATTR" name="EXEC_MSG_STALLED_ATTR" description="Cycles stalled trying to send a message to ATTR unit" units="cycles"/>
|
||||
<event offset="118" advanced="yes" counter="EXEC_INSTR_SLOT_1" title="EXEC_INSTR_SLOT_1" name="EXEC_INSTR_SLOT_1" description="Instructions issued in slot 1" units="instructions"/>
|
||||
<event offset="119" advanced="yes" counter="EXEC_ISSUE_SLOT_ANY" title="EXEC_ISSUE_SLOT_ANY" name="EXEC_ISSUE_SLOT_ANY" description="Clock cycles where instructions are issued in any slot" units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU_REQUESTS" name="MMU_REQUESTS" description="Number of requests received by the MMU" units="requests"/>
|
||||
<event offset="5" advanced="yes" counter="MMU_TABLE_READS_L3" title="MMU_TABLE_READS_L3" name="MMU_TABLE_READS_L3" description="Number of level 3 translation table reads" units="requests"/>
|
||||
<event offset="6" advanced="yes" counter="MMU_TABLE_READS_L2" title="MMU_TABLE_READS_L2" name="MMU_TABLE_READS_L2" description="Number of level 2 translation table reads" units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="MMU_HIT_L3" title="MMU_HIT_L3" name="MMU_HIT_L3" description="Number of hits to level 3 page descriptors" units="requests"/>
|
||||
<event offset="8" advanced="yes" counter="MMU_HIT_L2" title="MMU_HIT_L2" name="MMU_HIT_L2" description="Number of hits to level 2 page descriptors" units="requests"/>
|
||||
<event offset="12" advanced="yes" counter="L2_RD_MSG_IN_EVICT" title="L2_RD_MSG_IN_EVICT" name="L2_RD_MSG_IN_EVICT" description="Number of evict messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="13" advanced="yes" counter="L2_RD_MSG_IN_CU" title="L2_RD_MSG_IN_CU" name="L2_RD_MSG_IN_CU" description="Number of clean unique messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="14" advanced="yes" counter="L2_SNP_MSG_IN_SNPRSP" title="L2_SNP_MSG_IN_SNPRSP" name="L2_SNP_MSG_IN_SNPRSP" description="Number of snoop response messages without data received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="15" advanced="yes" counter="L2_RD_MSG_OUT_SNPREQ" title="L2_RD_MSG_OUT_SNPREQ" name="L2_RD_MSG_OUT_SNPREQ" description="Number of snoop request messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2_RD_MSG_IN" name="L2_RD_MSG_IN" description="Number of read messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2_RD_MSG_IN_STALL" name="L2_RD_MSG_IN_STALL" description="Number of cycles input read messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2_WR_MSG_IN" name="L2_WR_MSG_IN" description="Number of write messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2_WR_MSG_IN_STALL" name="L2_WR_MSG_IN_STALL" description="Number of cycles input write messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2_SNP_MSG_IN" name="L2_SNP_MSG_IN" description="Number of snoop messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2_SNP_MSG_IN_STALL" name="L2_SNP_MSG_IN_STALL" description="Number of cycles input snoop messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2_RD_MSG_OUT" name="L2_RD_MSG_OUT" description="Number of read messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2_RD_MSG_OUT_STALL" name="L2_RD_MSG_OUT_STALL" description="Number of cycles read messages that are stalled by internal requesters" units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2_WR_MSG_OUT" name="L2_WR_MSG_OUT" description="Number of write messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="25" advanced="yes" counter="L2_ANY_LOOKUP" title="L2_ANY_LOOKUP" name="L2_ANY_LOOKUP" description="Number of L2C lookups" units="requests"/>
|
||||
<event offset="26" advanced="yes" counter="L2_READ_LOOKUP" title="L2_READ_LOOKUP" name="L2_READ_LOOKUP" description="Number of L2C lookups performed by read transactions" units="transactions"/>
|
||||
<event offset="27" advanced="yes" counter="L2_WRITE_LOOKUP" title="L2_WRITE_LOOKUP" name="L2_WRITE_LOOKUP" description="Number of L2C lookups performed by write transactions" units="transactions"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2_EXT_SNOOP_LOOKUP" name="L2_EXT_SNOOP_LOOKUP" description="Number of L2C lookups performed by external snoop transactions" units="transactions"/>
|
||||
<event offset="29" advanced="yes" counter="L2_EXT_READ" title="L2_EXT_READ" name="L2_EXT_READ" description="Number of external read transactions" units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="L2_EXT_READ_NOSNP" name="L2_EXT_READ_NOSNP" description="Number of external ReadNoSnoop transactions" units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="L2_EXT_READ_UNIQUE" name="L2_EXT_READ_UNIQUE" description="Number of external ReadUnique or ReadOnce transactions" units="transactions"/>
|
||||
<event offset="32" advanced="yes" counter="L2_EXT_READ_BEATS" title="L2_EXT_READ_BEATS" name="L2_EXT_READ_BEATS" description="Number of external read data beats" units="beats"/>
|
||||
<event offset="33" advanced="yes" counter="L2_EXT_AR_STALL" title="L2_EXT_AR_STALL" name="L2_EXT_AR_STALL" description="Number of cycles read address (AR) is stalled" units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="L2_EXT_AR_CNT_Q1" title="L2_EXT_AR_CNT_Q1" name="L2_EXT_AR_CNT_Q1" description="Number of external read transactions when 0-25% outstanding" units="transactions"/>
|
||||
<event offset="35" advanced="yes" counter="L2_EXT_AR_CNT_Q2" title="L2_EXT_AR_CNT_Q2" name="L2_EXT_AR_CNT_Q2" description="Number of external read transactions when 25-50% outstanding" units="transactions"/>
|
||||
<event offset="36" advanced="yes" counter="L2_EXT_AR_CNT_Q3" title="L2_EXT_AR_CNT_Q3" name="L2_EXT_AR_CNT_Q3" description="Number of external read transactions when 50-75% outstanding" units="transactions"/>
|
||||
<event offset="37" advanced="yes" counter="L2_EXT_RRESP_0_127" title="L2_EXT_RRESP_0_127" name="L2_EXT_RRESP_0_127" description="Number of read responses with 0-127 cycle latency" units="cycles"/>
|
||||
<event offset="38" advanced="yes" counter="L2_EXT_RRESP_128_191" title="L2_EXT_RRESP_128_191" name="L2_EXT_RRESP_128_191" description="Number of read responses with 128-191 cycle latency" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="L2_EXT_RRESP_192_255" title="L2_EXT_RRESP_192_255" name="L2_EXT_RRESP_192_255" description="Number of read responses with 192-255 cycle latency" units="cycles"/>
|
||||
<event offset="40" advanced="yes" counter="L2_EXT_RRESP_256_319" title="L2_EXT_RRESP_256_319" name="L2_EXT_RRESP_256_319" description="Number of read responses with 256-319 cycle latency" units="cycles"/>
|
||||
<event offset="41" advanced="yes" counter="L2_EXT_RRESP_320_383" title="L2_EXT_RRESP_320_383" name="L2_EXT_RRESP_320_383" description="Number of read responses with 320-383 cycle latency" units="cycles"/>
|
||||
<event offset="42" advanced="yes" counter="L2_EXT_WRITE" title="L2_EXT_WRITE" name="L2_EXT_WRITE" description="Number of external write transactions" units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="L2_EXT_WRITE_NOSNP_FULL" name="L2_EXT_WRITE_NOSNP_FULL" description="Number of external WriteNoSnpFull transactions" units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="L2_EXT_WRITE_NOSNP_PTL" name="L2_EXT_WRITE_NOSNP_PTL" description="Number of external WriteNoSnpPtl transactions" units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="L2_EXT_WRITE_SNP_FULL" name="L2_EXT_WRITE_SNP_FULL" description="Number of external WriteBackFull or WriteUniqueFull transactions" units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="L2_EXT_WRITE_SNP_PTL" name="L2_EXT_WRITE_SNP_PTL" description="Number of external WriteBackPtl or WriteUniquePtl transactions" units="transactions"/>
|
||||
<event offset="47" advanced="yes" counter="L2_EXT_WRITE_BEATS" title="L2_EXT_WRITE_BEATS" name="L2_EXT_WRITE_BEATS" description="Number of external write data beats" units="beats"/>
|
||||
<event offset="48" advanced="yes" counter="L2_EXT_W_STALL" title="L2_EXT_W_STALL" name="L2_EXT_W_STALL" description="Number of cycles write data (W) is stalled" units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="L2_EXT_AW_CNT_Q1" title="L2_EXT_AW_CNT_Q1" name="L2_EXT_AW_CNT_Q1" description="Number of external write transactions when the write buffer is 0-25% full" units="transactions"/>
|
||||
<event offset="50" advanced="yes" counter="L2_EXT_AW_CNT_Q2" title="L2_EXT_AW_CNT_Q2" name="L2_EXT_AW_CNT_Q2" description="Number of external write transactions when the write buffer is 25-50% full" units="transactions"/>
|
||||
<event offset="51" advanced="yes" counter="L2_EXT_AW_CNT_Q3" title="L2_EXT_AW_CNT_Q3" name="L2_EXT_AW_CNT_Q3" description="Number of external write transactions when the write buffer is 50-75% full" units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="L2_EXT_SNOOP" name="L2_EXT_SNOOP" description="Number of external snoop transactions" units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="L2_EXT_SNOOP_STALL" name="L2_EXT_SNOOP_STALL" description="Number of cycles external snoop requests are stalled" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="L2_EXT_SNOOP_RESP_CLEAN" title="L2_EXT_SNOOP_RESP_CLEAN" name="L2_EXT_SNOOP_RESP_CLEAN" description="Number of external snoops that hit a clean line in the Level 2 cache" units="requests"/>
|
||||
<event offset="55" advanced="yes" counter="L2_EXT_SNOOP_RESP_DATA" title="L2_EXT_SNOOP_RESP_DATA" name="L2_EXT_SNOOP_RESP_DATA" description="Number of external snoops that hit in the Level 2 cache and return data" units="requests"/>
|
||||
<event offset="56" advanced="yes" counter="L2_EXT_SNOOP_INTERNAL" title="L2_EXT_SNOOP_INTERNAL" name="L2_EXT_SNOOP_INTERNAL" description="Number of external snoops that cause snoops to Level 1 caches" units="requests"/>
|
||||
<event offset="59" advanced="yes" counter="L2_CE_MSG_IN" title="L2_CE_MSG_IN" name="L2_CE_MSG_IN" description="Number of internal clean engine messages" units="requests"/>
|
||||
<event offset="60" advanced="yes" counter="L2_CE_LOOKUP" title="L2_CE_LOOKUP" name="L2_CE_LOOKUP" description="Number of lookups performed by clean engine flush transactions" units="transactions"/>
|
||||
<event offset="61" advanced="yes" counter="L2_CE_WB" title="L2_CE_WB" name="L2_CE_WB" description="Number of write-backs caused by clean engine flush transaction" units="transactions"/>
|
||||
<event offset="62" advanced="yes" counter="L2_CE_REPLAY" title="L2_CE_REPLAY" name="L2_CE_REPLAY" description="Number of replayed clean engine flush transactions" units="transactions"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
pan_hw_metrics = [
|
||||
'G31', 'G51', 'G52', 'G57', 'G68', 'G71', 'G72', 'G76', 'G77',
|
||||
'Gx10', 'G78', 'T72x', 'T76x', 'T82x', 'T83x', 'T86x', 'T88x',
|
||||
'Gx10', 'Gx25', 'G78', 'T72x', 'T76x', 'T82x', 'T83x', 'T86x', 'T88x',
|
||||
]
|
||||
|
||||
pan_hw_metrics_xml_files = []
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PAN_PERF_MAX_COUNTERS 64
|
||||
#define PAN_PERF_MAX_COUNTERS 128
|
||||
|
||||
enum pan_perf_counter_categories {
|
||||
PAN_PERF_COUNTER_CAT_FRONTEND,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue