diff --git a/.pick_status.json b/.pick_status.json
index 38519e7bf31..ebc0336b60a 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -67,7 +67,7 @@
         "description": "isl: drop min row pitch alignment when set by the driver",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "a3f6db2c4e927be7e7d40cbc39c8664030d2af59"
     },
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 040d3f38906..195099e6d4b 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1368,11 +1368,19 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
    if (tile_info->tiling != ISL_TILING_LINEAR) {
       /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches must
        * be 512B-aligned. CCS is only support on Y tilings.
+       *
+       * Only consider 512B alignment when :
+       *    - AUX is not explicitly disabled
+       *    - the caller has specified no pitch
+       *
+       * isl_surf_get_ccs_surf() will check that the main surface alignment
+       * matches CCS expectations.
        */
       if (ISL_DEV_GEN(dev) >= 12 &&
           isl_format_supports_ccs_e(dev->info, surf_info->format) &&
           tile_info->tiling != ISL_TILING_X &&
-          !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
+          !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
+          surf_info->row_pitch_B == 0) {
          return isl_align(tile_info->phys_extent_B.width, 512);
       }