From 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 2 Mar 2022 17:11:10 -0800
Subject: [PATCH] freedreno/registers: Add a couple regs we need for kernel

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221>
---
 src/freedreno/.gitlab-ci/reference/crash.log  | 2 +-
 src/freedreno/registers/adreno/a6xx.xml       | 2 ++
 src/freedreno/registers/adreno/adreno_pm4.xml | 3 +++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 45edfb3aeb7..e5cbf182091 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -590,7 +590,7 @@ registers:
 	00000000	RBBM_PERFCTR_RBBM_SEL[0x2]+0: 00000000
 	00000000	RBBM_PERFCTR_RBBM_SEL[0x3]+0: 00000000
 	002f7fff	RBBM_PERFCTR_GPU_BUSY_MASKED: 0x2f7fff
-	00000000	0x50f: 00000000
+	00000000	RBBM_PERFCTR_SRAM_INIT_STATUS: 0
 	00000000	0x511: 00000000
 	00000000	RBBM_ISDB_CNT: 0
 	80108000	RBBM_PRIMCTR_0_LO: 0x80108000
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 2bf482fd316..006bd7180ed 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1165,6 +1165,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
 	<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
 	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
+	<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
+	<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
 	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
 
 	<!---
diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml
index c53f6a2d069..7b898709ab9 100644
--- a/src/freedreno/registers/adreno/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno/adreno_pm4.xml
@@ -455,6 +455,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="CP_WAIT_TWO_REGS" value="0x70" varset="chip" variants="A6XX"/>
 	<value name="CP_MEMCPY" value="0x75" varset="chip" variants="A6XX"/>
 	<value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" varset="chip" variants="A6XX"/>
+	<!-- Note, kgsl calls this CP_SET_AMBLE: -->
 	<value name="CP_SET_CTXSWITCH_IB" value="0x55" varset="chip" variants="A6XX"/>
 
 	<!--
@@ -1703,6 +1704,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 				This can only be set by the RB (i.e. the kernel)
 				and executes with protected mode off, but
 				is otherwise similar to SAVE_IB.
+
+				Note, kgsl calls this CP_KMD_AMBLE_TYPE
 			</doc>
 		</value>
 	</enum>