From 7e433e25c82607b7e2f4424d51eef4eaa8807915 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 15 Sep 2022 14:55:59 +0200 Subject: [PATCH] radv: add nir_intrinsic_load_sample_positions_amd in the ABI Signed-off-by: Samuel Pitoiset Reviewed-by: Rhys Perry Part-of: --- src/amd/vulkan/radv_nir_lower_abi.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index a03e5164056..ed77952da3d 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -254,6 +254,27 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) } break; } + case nir_intrinsic_load_sample_positions_amd: { + uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16; + + nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, s->args->ring_offsets); + nir_ssa_def *addr = nir_pack_64_2x32(b, ring_offsets); + nir_ssa_def *sample_id = nir_umin(b, intrin->src[0].ssa, nir_imm_int(b, 7)); + nir_ssa_def *offset = nir_ishl_imm(b, sample_id, 3); /* 2 floats containing samplepos.xy */ + + if (s->pl_key->ps.num_samples == 2) { + sample_pos_offset += 1 << 3; + } else if (s->pl_key->ps.num_samples == 4) { + sample_pos_offset += 3 << 3; + } else { + assert(s->pl_key->ps.num_samples == 8); + sample_pos_offset += 7 << 3; + } + + replacement = nir_load_global_amd(b, 2, 32, addr, offset, + .base = sample_pos_offset, .access = ACCESS_NON_WRITEABLE); + break; + } default: break; }