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nak,nir: Drop r2ur_nv in favor of as_uniform

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29737>
This commit is contained in:
Faith Ekstrand 2024-06-14 15:44:38 -05:00 • committed by Marge Bot
parent f7434d7576
commit 7e3d157bee
4 changed files with 15 additions and 19 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
View file

@ -267,7 +267,6 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_optimization_barrier_sgpr_amd:
case nir_intrinsic_load_printf_buffer_address:
case nir_intrinsic_load_printf_base_identifier:
case nir_intrinsic_r2ur_nv:
is_divergent = false;
break;

3
src/compiler/nir/nir_intrinsics.py
View file

@ -2229,9 +2229,6 @@ intrinsic("ldc_nv", dest_comp=0, src_comp=[1, 1],
# src[] = { handle }.
intrinsic("pin_cx_handle_nv", src_comp=[1])
intrinsic("unpin_cx_handle_nv", src_comp=[1])
# Explicitly copies a value to a uniform register
intrinsic("r2ur_nv", dest_comp=0, src_comp=[0],
flags=[CAN_ELIMINATE, CAN_REORDER])
# src[] = { handle, offset }.
intrinsic("ldcx_nv", dest_comp=0, src_comp=[1, 1],
indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET],

26
src/nouveau/compiler/nak/from_nir.rs
View file

@ -2054,6 +2054,19 @@ impl<'a> ShaderFromNir<'a> {
panic!("Invalid VTG I/O intrinsic");
}
}
nir_intrinsic_as_uniform => {
let src = self.get_ssa(srcs[0].as_def());
let mut dst = Vec::new();
for comp in src {
let u = b.alloc_ssa(RegFile::UGPR, 1);
b.push_op(OpR2UR {
src: [*comp].into(),
dst: u.into(),
});
dst.push(u[0]);
}
self.set_ssa(&intrin.def, dst);
}
nir_intrinsic_ballot => {
assert!(srcs[0].bit_size() == 1);
let src = self.get_src(&srcs[0]);
@ -2821,19 +2834,6 @@ impl<'a> ShaderFromNir<'a> {
});
self.set_dst(&intrin.def, dst);
}
nir_intrinsic_r2ur_nv => {
let src = self.get_ssa(srcs[0].as_def());
let mut dst = Vec::new();
for comp in src {
let u = b.alloc_ssa(RegFile::UGPR, 1);
b.push_op(OpR2UR {
src: [*comp].into(),
dst: u.into(),
});
dst.push(u[0]);
}
self.set_ssa(&intrin.def, dst);
}
nir_intrinsic_shared_atomic => {
let bit_size = intrin.def.bit_size();
let (addr, offset) = self.get_io_addr_offset(&srcs[0], 24);

4
src/nouveau/compiler/nak_nir_lower_non_uniform_ldcx.c
View file

@ -281,7 +281,7 @@ sort_and_mark_live_handles(nir_builder *b, struct non_uniform_section *nus)
for (unsigned i = 0; i < num_handles && i < max_live_handles; i++) {
nir_def *handle = handles[i].handle;
if (handle->divergent)
handle = nir_r2ur_nv(b, 64, handles[i].handle);
handle = nir_as_uniform(b, handles[i].handle);
nir_pin_cx_handle_nv(b, handle);
_mesa_hash_table_insert(nus->live_handles, handle, handle);
@ -368,7 +368,7 @@ lower_ldcx_block(nir_builder *b, nir_block *block,
progress = true;
} else if (handle->divergent) {
b->cursor = nir_before_instr(&load->instr);
nir_def *ugpr = nir_r2ur_nv(b, 64, handle);
nir_def *ugpr = nir_as_uniform(b, handle);
nir_src_rewrite(&load->src[0], ugpr);
progress = true;
}