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v3dv: use vk_graphics_pipeline_state for pipeline creation

Browse source 
Refactor pipeline creation path to use the vk_graphics_pipeline_state
structures provided by runtime instead of raw Vulkan CreateInfo structs.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39834>
This commit is contained in:
Daivik Bhatia 2026-02-11 06:34:12 +05:30 • committed by Marge Bot
parent 2b5b41bb24
commit 7e2693f3d3
3 changed files with 100 additions and 179 deletions
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165
src/broadcom/vulkan/v3dv_pipeline.c
View file

@ -1065,18 +1065,12 @@ static const enum pipe_logicop vk_to_pipe_logicop[] = {
static bool
enable_line_smooth(struct v3dv_pipeline *pipeline,
const VkPipelineRasterizationStateCreateInfo *rs_info)
const struct vk_rasterization_state *rs)
{
if (!pipeline->rasterization_enabled)
return false;
assert(rs_info);
const VkPipelineRasterizationLineStateCreateInfoKHR *ls_info =
vk_find_struct_const(rs_info->pNext,
PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_KHR);
if (!ls_info)
return false;
assert(rs);
enum mesa_prim output_topology;
if (pipeline->has_gs) {
@ -1097,7 +1091,7 @@ enable_line_smooth(struct v3dv_pipeline *pipeline,
case MESA_PRIM_LINE_STRIP:
case MESA_PRIM_LINES_ADJACENCY:
case MESA_PRIM_LINE_STRIP_ADJACENCY:
return ls_info->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR;
return rs->line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_KHR;
default:
return false;
}
@ -1170,7 +1164,7 @@ v3d_fs_key_set_color_attachment(struct v3d_fs_key *key,
static void
pipeline_populate_v3d_fs_key(struct v3d_fs_key *key,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct vk_graphics_pipeline_state *state,
const struct vk_render_pass_state *rendering_info,
const struct v3dv_pipeline_stage *p_stage,
bool has_geometry_shader,
@ -1197,9 +1191,9 @@ pipeline_populate_v3d_fs_key(struct v3d_fs_key *key,
*/
key->ucp_enables = ucp_enables;
const VkPipelineInputAssemblyStateCreateInfo *ia_info =
pCreateInfo->pInputAssemblyState;
uint8_t topology = vk_topology_to_mesa(ia_info->topology);
const struct vk_input_assembly_state *ia = state->ia;
assert(ia);
uint8_t topology = vk_topology_to_mesa(ia->primitive_topology);
key->is_points = (topology == MESA_PRIM_POINTS);
key->is_lines = (topology >= MESA_PRIM_LINES &&
@ -1217,32 +1211,29 @@ pipeline_populate_v3d_fs_key(struct v3d_fs_key *key,
key->has_gs = has_geometry_shader;
const VkPipelineColorBlendStateCreateInfo *cb_info =
p_stage->pipeline->rasterization_enabled ?
pCreateInfo->pColorBlendState : NULL;
const struct vk_color_blend_state *cb_info = state->cb;
key->logicop_func = cb_info && cb_info->logicOpEnable == VK_TRUE ?
vk_to_pipe_logicop[cb_info->logicOp] :
key->logicop_func = cb_info && cb_info->logic_op_enable ?
vk_to_pipe_logicop[cb_info->logic_op] :
PIPE_LOGICOP_COPY;
/* Multisample rasterization state must be ignored if rasterization
* is disabled.
*/
const VkPipelineMultisampleStateCreateInfo *ms_info =
p_stage->pipeline->rasterization_enabled ? pCreateInfo->pMultisampleState : NULL;
const struct vk_multisample_state *ms_info = state->ms;
if (ms_info) {
assert(ms_info->rasterizationSamples == VK_SAMPLE_COUNT_1_BIT ||
ms_info->rasterizationSamples == VK_SAMPLE_COUNT_4_BIT);
key->msaa = ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT;
assert(ms_info->rasterization_samples == VK_SAMPLE_COUNT_1_BIT ||
ms_info->rasterization_samples == VK_SAMPLE_COUNT_4_BIT);
key->msaa = ms_info->rasterization_samples > VK_SAMPLE_COUNT_1_BIT;
if (key->msaa)
key->sample_alpha_to_coverage = ms_info->alphaToCoverageEnable;
key->sample_alpha_to_coverage = ms_info->alpha_to_coverage_enable;
key->sample_alpha_to_one = ms_info->alphaToOneEnable;
key->sample_alpha_to_one = ms_info->alpha_to_one_enable;
}
key->line_smoothing = enable_line_smooth(p_stage->pipeline,
pCreateInfo->pRasterizationState);
const struct vk_rasterization_state *rs = state->rs;
key->line_smoothing = enable_line_smooth(p_stage->pipeline, rs);
/* This is intended for V3D versions before 4.1, otherwise we just use the
* tile buffer load/store swap R/B bit.
@ -1273,7 +1264,6 @@ setup_stage_outputs_from_next_stage_inputs(
static void
pipeline_populate_v3d_gs_key(struct v3d_gs_key *key,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct v3dv_pipeline_stage *p_stage)
{
assert(p_stage->stage == BROADCOM_SHADER_GEOMETRY ||
@ -1925,8 +1915,7 @@ pipeline_compile_vertex_shader(struct v3dv_pipeline *pipeline,
static VkResult
pipeline_compile_geometry_shader(struct v3dv_pipeline *pipeline,
const VkAllocationCallbacks *pAllocator,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
const VkAllocationCallbacks *pAllocator)
{
struct v3dv_pipeline_stage *p_stage_gs =
pipeline->stages[BROADCOM_SHADER_GEOMETRY];
@ -1942,14 +1931,14 @@ pipeline_compile_geometry_shader(struct v3dv_pipeline *pipeline,
VkResult vk_result;
struct v3d_gs_key key;
pipeline_populate_v3d_gs_key(&key, pCreateInfo, p_stage_gs);
pipeline_populate_v3d_gs_key(&key, p_stage_gs);
pipeline->shared_data->variants[BROADCOM_SHADER_GEOMETRY] =
pipeline_compile_shader_variant(p_stage_gs, &key.base, sizeof(key),
pAllocator, &vk_result);
if (vk_result != VK_SUCCESS)
return vk_result;
pipeline_populate_v3d_gs_key(&key, pCreateInfo, p_stage_gs_bin);
pipeline_populate_v3d_gs_key(&key, p_stage_gs_bin);
pipeline->shared_data->variants[BROADCOM_SHADER_GEOMETRY_BIN] =
pipeline_compile_shader_variant(p_stage_gs_bin, &key.base, sizeof(key),
pAllocator, &vk_result);
@ -1960,7 +1949,7 @@ pipeline_compile_geometry_shader(struct v3dv_pipeline *pipeline,
static VkResult
pipeline_compile_fragment_shader(struct v3dv_pipeline *pipeline,
const VkAllocationCallbacks *pAllocator,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
const struct vk_graphics_pipeline_state *state)
{
struct v3dv_pipeline_stage *p_stage_vs =
pipeline->stages[BROADCOM_SHADER_VERTEX];
@ -1970,7 +1959,7 @@ pipeline_compile_fragment_shader(struct v3dv_pipeline *pipeline,
pipeline->stages[BROADCOM_SHADER_GEOMETRY];
struct v3d_fs_key key;
pipeline_populate_v3d_fs_key(&key, pCreateInfo, &pipeline->rendering_info,
pipeline_populate_v3d_fs_key(&key, state, &pipeline->rendering_info,
p_stage_fs, p_stage_gs != NULL,
get_ucp_enable_mask(p_stage_vs));
@ -1990,7 +1979,8 @@ pipeline_compile_fragment_shader(struct v3dv_pipeline *pipeline,
static void
pipeline_populate_graphics_key(struct v3dv_pipeline *pipeline,
struct v3dv_pipeline_key *key,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct vk_graphics_pipeline_state *state)
{
struct v3dv_device *device = pipeline->device;
assert(device);
@ -1999,31 +1989,29 @@ pipeline_populate_graphics_key(struct v3dv_pipeline *pipeline,
key->line_smooth = pipeline->line_smooth;
const VkPipelineInputAssemblyStateCreateInfo *ia_info =
pCreateInfo->pInputAssemblyState;
key->topology = vk_topology_to_mesa(ia_info->topology);
const struct vk_input_assembly_state *ia = state->ia;
assert(ia);
key->topology = vk_topology_to_mesa(ia->primitive_topology);
const VkPipelineColorBlendStateCreateInfo *cb_info =
pipeline->rasterization_enabled ? pCreateInfo->pColorBlendState : NULL;
const struct vk_color_blend_state *cb_info = state->cb;
key->logicop_func = cb_info && cb_info->logicOpEnable == VK_TRUE ?
vk_to_pipe_logicop[cb_info->logicOp] :
key->logicop_func = cb_info && cb_info->logic_op_enable ?
vk_to_pipe_logicop[cb_info->logic_op] :
PIPE_LOGICOP_COPY;
/* Multisample rasterization state must be ignored if rasterization
* is disabled.
*/
const VkPipelineMultisampleStateCreateInfo *ms_info =
pipeline->rasterization_enabled ? pCreateInfo->pMultisampleState : NULL;
const struct vk_multisample_state *ms_info = state->ms;
if (ms_info) {
assert(ms_info->rasterizationSamples == VK_SAMPLE_COUNT_1_BIT ||
ms_info->rasterizationSamples == VK_SAMPLE_COUNT_4_BIT);
key->msaa = ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT;
assert(ms_info->rasterization_samples == VK_SAMPLE_COUNT_1_BIT ||
ms_info->rasterization_samples == VK_SAMPLE_COUNT_4_BIT);
key->msaa = ms_info->rasterization_samples > VK_SAMPLE_COUNT_1_BIT;
if (key->msaa)
key->sample_alpha_to_coverage = ms_info->alphaToCoverageEnable;
key->sample_alpha_to_coverage = ms_info->alpha_to_coverage_enable;
key->sample_alpha_to_one = ms_info->alphaToOneEnable;
key->sample_alpha_to_one = ms_info->alpha_to_one_enable;
}
key->software_blend = pipeline->blend.use_software;
@ -2427,6 +2415,7 @@ pipeline_check_buffer_device_address(struct v3dv_pipeline *pipeline)
static VkResult
pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
struct v3dv_pipeline_cache *cache,
const struct vk_graphics_pipeline_state *state,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const VkAllocationCallbacks *pAllocator)
{
@ -2548,7 +2537,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
pipeline->flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR;
if (!needs_executable_info) {
struct v3dv_pipeline_key pipeline_key;
pipeline_populate_graphics_key(pipeline, &pipeline_key, pCreateInfo);
pipeline_populate_graphics_key(pipeline, &pipeline_key, pCreateInfo, state);
pipeline_hash_graphics(pipeline, &pipeline_key, pipeline->sha1);
bool cache_hit = false;
@ -2631,7 +2620,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
/* We should have got all the variants or no variants from the cache */
assert(!pipeline->shared_data->variants[BROADCOM_SHADER_FRAGMENT]);
vk_result = pipeline_compile_fragment_shader(pipeline, pAllocator,
pCreateInfo);
state);
if (vk_result != VK_SUCCESS)
return vk_result;
@ -2640,7 +2629,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
if (p_stage_gs) {
vk_result =
pipeline_compile_geometry_shader(pipeline, pAllocator, pCreateInfo);
pipeline_compile_geometry_shader(pipeline, pAllocator);
if (vk_result != VK_SUCCESS)
return vk_result;
}
@ -2770,26 +2759,25 @@ v3dv_compute_ez_state(struct vk_dynamic_graphics_state *dyn,
static void
pipeline_set_sample_mask(struct v3dv_pipeline *pipeline,
const VkPipelineMultisampleStateCreateInfo *ms_info)
const struct vk_multisample_state *ms)
{
pipeline->sample_mask = (1 << V3D_MAX_SAMPLES) - 1;
/* Ignore pSampleMask if we are not enabling multisampling. The hardware
* requires this to be 0xf or 0x0 if using a single sample.
*/
if (ms_info && ms_info->pSampleMask &&
ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT) {
pipeline->sample_mask &= ms_info->pSampleMask[0];
if (ms && ms->rasterization_samples > VK_SAMPLE_COUNT_1_BIT) {
pipeline->sample_mask &= ms->sample_mask;
}
}
static void
pipeline_set_sample_rate_shading(struct v3dv_pipeline *pipeline,
const VkPipelineMultisampleStateCreateInfo *ms_info)
const struct vk_multisample_state *ms)
{
pipeline->sample_rate_shading =
ms_info && ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT &&
ms_info->sampleShadingEnable;
ms && ms->rasterization_samples > VK_SAMPLE_COUNT_1_BIT &&
ms->sample_shading_enable;
}
static void
@ -2946,10 +2934,6 @@ pipeline_init(struct v3dv_pipeline *pipeline,
pipeline_setup_rendering_info(device, pipeline, pCreateInfo, pAllocator);
const VkPipelineInputAssemblyStateCreateInfo *ia_info =
pCreateInfo->pInputAssemblyState;
pipeline->topology = vk_topology_to_mesa(ia_info->topology);
struct vk_graphics_pipeline_all_state all;
struct vk_graphics_pipeline_state pipeline_state = { };
result = pipeline_init_dynamic_state(device, pipeline, &all, &pipeline_state,
@ -2962,6 +2946,10 @@ pipeline_init(struct v3dv_pipeline *pipeline,
return result;
}
const struct vk_input_assembly_state *ia = pipeline_state.ia;
assert(ia);
pipeline->topology = vk_topology_to_mesa(ia->primitive_topology);
/* If rasterization is disabled, we just disable it through the CFG_BITS
* packet, so for building the pipeline we always assume it is enabled
*/
@ -2971,51 +2959,18 @@ pipeline_init(struct v3dv_pipeline *pipeline,
pipeline->rasterization_enabled = raster_enabled;
const VkPipelineViewportStateCreateInfo *vp_info =
raster_enabled ? pCreateInfo->pViewportState : NULL;
if (raster_enabled && pipeline_state.vp)
pipeline->negative_one_to_one =
pipeline_state.vp->depth_clip_negative_one_to_one;
const VkPipelineDepthStencilStateCreateInfo *ds_info =
raster_enabled ? pCreateInfo->pDepthStencilState : NULL;
v3d_X((&device->devinfo), pipeline_pack_state)(pipeline, &pipeline_state);
const VkPipelineRasterizationStateCreateInfo *rs_info =
raster_enabled ? pCreateInfo->pRasterizationState : NULL;
pipeline_set_sample_mask(pipeline, pipeline_state.ms);
pipeline_set_sample_rate_shading(pipeline, pipeline_state.ms);
pipeline->line_smooth = enable_line_smooth(pipeline, pipeline_state.rs);
const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info =
raster_enabled ? vk_find_struct_const(
rs_info->pNext,
PIPELINE_RASTERIZATION_PROVOKING_VERTEX_STATE_CREATE_INFO_EXT) :
NULL;
const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info =
raster_enabled ? vk_find_struct_const(
rs_info->pNext,
PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT) :
NULL;
const VkPipelineColorBlendStateCreateInfo *cb_info =
raster_enabled ? pCreateInfo->pColorBlendState : NULL;
const VkPipelineMultisampleStateCreateInfo *ms_info =
raster_enabled ? pCreateInfo->pMultisampleState : NULL;
const VkPipelineViewportDepthClipControlCreateInfoEXT *depth_clip_control =
vp_info ? vk_find_struct_const(vp_info->pNext,
PIPELINE_VIEWPORT_DEPTH_CLIP_CONTROL_CREATE_INFO_EXT) :
NULL;
if (depth_clip_control)
pipeline->negative_one_to_one = depth_clip_control->negativeOneToOne;
v3d_X((&device->devinfo), pipeline_pack_state)(pipeline, cb_info, ds_info,
rs_info, pv_info, ls_info,
ms_info,
&pipeline_state);
pipeline_set_sample_mask(pipeline, ms_info);
pipeline_set_sample_rate_shading(pipeline, ms_info);
pipeline->line_smooth = enable_line_smooth(pipeline, rs_info);
result = pipeline_compile_graphics(pipeline, cache, pCreateInfo, pAllocator);
result = pipeline_compile_graphics(pipeline, cache, &pipeline_state,
pCreateInfo, pAllocator);
if (result != VK_SUCCESS) {
/* Caller would already destroy the pipeline, and we didn't allocate any

108
src/broadcom/vulkan/v3dvx_pipeline.c
View file

@ -71,7 +71,7 @@ blend_factor(VkBlendFactor factor, bool dst_alpha_one, bool *needs_constants,
static void
pack_blend(struct v3dv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *cb_info)
const struct vk_color_blend_state *cb)
{
/* By default, we are not enabling blending and all color channel writes are
* enabled. Color write enables are independent of whether blending is
@ -83,30 +83,30 @@ pack_blend(struct v3dv_pipeline *pipeline,
pipeline->blend.enables = 0;
pipeline->blend.color_write_masks = 0; /* All channels enabled */
if (!cb_info)
if (!cb)
return;
const struct vk_render_pass_state *ri = &pipeline->rendering_info;
if (ri->color_attachment_count == 0)
return;
assert(ri->color_attachment_count == cb_info->attachmentCount);
assert(ri->color_attachment_count == cb->attachment_count);
pipeline->blend.needs_color_constants = false;
uint32_t color_write_masks = 0;
bool needs_dual_src = false;
for (uint32_t i = 0; i < ri->color_attachment_count; i++) {
const VkPipelineColorBlendAttachmentState *b_state =
&cb_info->pAttachments[i];
const struct vk_color_blend_attachment_state *b_state =
&cb->attachments[i];
const VkFormat vk_format = ri->color_attachment_formats[i];
if (vk_format == VK_FORMAT_UNDEFINED)
continue;
color_write_masks |= (~b_state->colorWriteMask & 0xf) << (4 * i);
color_write_masks |= (~b_state->write_mask & 0xf) << (4 * i);
/* Vulkan requires ignoring blending if logic operations are enabled */
if (!b_state->blendEnable || cb_info->logicOpEnable)
if (!b_state->blend_enable || cb->logic_op_enable)
continue;
const struct v3dv_format *format = v3dX(get_format)(vk_format);
@ -123,23 +123,23 @@ pack_blend(struct v3dv_pipeline *pipeline,
v3dvx_pack(pipeline->blend.cfg[i], BLEND_CFG, config) {
config.render_target_mask = rt_mask;
config.color_blend_mode = b_state->colorBlendOp;
config.color_blend_mode = b_state->color_blend_op;
config.color_blend_dst_factor =
blend_factor(b_state->dstColorBlendFactor, dst_alpha_one,
blend_factor(b_state->dst_color_blend_factor, dst_alpha_one,
&pipeline->blend.needs_color_constants,
&needs_dual_src);
config.color_blend_src_factor =
blend_factor(b_state->srcColorBlendFactor, dst_alpha_one,
blend_factor(b_state->src_color_blend_factor, dst_alpha_one,
&pipeline->blend.needs_color_constants,
&needs_dual_src);
config.alpha_blend_mode = b_state->alphaBlendOp;
config.alpha_blend_mode = b_state->alpha_blend_op;
config.alpha_blend_dst_factor =
blend_factor(b_state->dstAlphaBlendFactor, dst_alpha_one,
blend_factor(b_state->dst_alpha_blend_factor, dst_alpha_one,
&pipeline->blend.needs_color_constants,
&needs_dual_src);
config.alpha_blend_src_factor =
blend_factor(b_state->srcAlphaBlendFactor, dst_alpha_one,
blend_factor(b_state->src_alpha_blend_factor, dst_alpha_one,
&pipeline->blend.needs_color_constants,
&needs_dual_src);
}
@ -157,32 +157,29 @@ pack_blend(struct v3dv_pipeline *pipeline,
*/
static void
pack_cfg_bits(struct v3dv_pipeline *pipeline,
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const VkPipelineRasterizationStateCreateInfo *rs_info,
const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info,
const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info,
const VkPipelineMultisampleStateCreateInfo *ms_info)
const struct vk_rasterization_state *rs,
const struct vk_multisample_state *ms)
{
assert(sizeof(pipeline->cfg_bits) == cl_packet_length(CFG_BITS));
pipeline->msaa =
ms_info && ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT;
ms && ms->rasterization_samples > VK_SAMPLE_COUNT_1_BIT;
v3dvx_pack(pipeline->cfg_bits, CFG_BITS, config) {
/* This is required to pass line rasterization tests in CTS while
* exposing, at least, a minimum of 4-bits of subpixel precision
* (the minimum requirement).
*/
if (ls_info &&
ls_info->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT)
if (rs &&
rs->line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT)
config.line_rasterization = V3D_LINE_RASTERIZATION_DIAMOND_EXIT;
else
config.line_rasterization = V3D_LINE_RASTERIZATION_PERP_END_CAPS;
if (rs_info && rs_info->polygonMode != VK_POLYGON_MODE_FILL) {
if (rs && rs->polygon_mode != VK_POLYGON_MODE_FILL) {
config.direct3d_wireframe_triangles_mode = true;
config.direct3d_point_fill_mode =
rs_info->polygonMode == VK_POLYGON_MODE_POINT;
rs->polygon_mode == VK_POLYGON_MODE_POINT;
}
/* diamond-exit rasterization does not support oversample */
@ -201,13 +198,8 @@ pack_cfg_bits(struct v3dv_pipeline *pipeline,
* First vertex is the Direct3D style for provoking vertex. OpenGL uses
* the last vertex by default.
*/
if (pv_info) {
config.direct3d_provoking_vertex =
pv_info->provokingVertexMode ==
VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT;
} else {
config.direct3d_provoking_vertex = true;
}
config.direct3d_provoking_vertex = !rs ||
rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT;
config.blend_enable = pipeline->blend.enables != 0 &&
!pipeline->blend.use_software;
@ -223,16 +215,8 @@ pack_cfg_bits(struct v3dv_pipeline *pipeline,
* Otherwise depth clipping is controlled by the state set in
* VkPipelineRasterizationDepthClipStateCreateInfoEXT."
*/
bool z_clamp_enable = rs_info && rs_info->depthClampEnable;
bool z_clip_enable = false;
const VkPipelineRasterizationDepthClipStateCreateInfoEXT *clip_info =
rs_info ? vk_find_struct_const(rs_info->pNext,
PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT) :
NULL;
if (clip_info)
z_clip_enable = clip_info->depthClipEnable;
else if (!z_clamp_enable)
z_clip_enable = true;
bool z_clamp_enable = rs && rs->depth_clamp_enable;
bool z_clip_enable = rs && vk_rasterization_state_depth_clip_enable(rs);
if (z_clip_enable) {
config.z_clipping_mode = pipeline->negative_one_to_one ?
@ -276,8 +260,7 @@ pack_single_stencil_cfg(struct v3dv_pipeline *pipeline,
uint8_t *stencil_cfg,
bool is_front,
bool is_back,
const VkStencilOpState *stencil_state,
const struct vk_graphics_pipeline_state *state)
const struct vk_stencil_test_face_state *stencil_state)
{
/* From the Vulkan spec:
*
@ -293,27 +276,26 @@ pack_single_stencil_cfg(struct v3dv_pipeline *pipeline,
v3dvx_pack(stencil_cfg, STENCIL_CFG, config) {
config.front_config = is_front;
config.back_config = is_back;
config.stencil_write_mask = stencil_state->writeMask & 0xff;
config.stencil_test_mask = stencil_state->compareMask & 0xff;
config.stencil_test_function = stencil_state->compareOp;
config.stencil_write_mask = stencil_state->write_mask & 0xff;
config.stencil_test_mask = stencil_state->compare_mask & 0xff;
config.stencil_test_function = stencil_state->op.compare;
config.stencil_pass_op =
v3dX(translate_stencil_op)(stencil_state->passOp);
v3dX(translate_stencil_op)(stencil_state->op.pass);
config.depth_test_fail_op =
v3dX(translate_stencil_op)(stencil_state->depthFailOp);
v3dX(translate_stencil_op)(stencil_state->op.depth_fail);
config.stencil_test_fail_op =
v3dX(translate_stencil_op)(stencil_state->failOp);
v3dX(translate_stencil_op)(stencil_state->op.fail);
config.stencil_ref_value = stencil_state->reference & 0xff;
}
}
static void
pack_stencil_cfg(struct v3dv_pipeline *pipeline,
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const struct vk_graphics_pipeline_state *state)
{
assert(sizeof(pipeline->stencil_cfg) == 2 * cl_packet_length(STENCIL_CFG));
if (!ds_info || !ds_info->stencilTestEnable)
if (!state->ds || !state->ds->stencil.test_enable)
return;
const struct vk_render_pass_state *ri = &pipeline->rendering_info;
@ -332,7 +314,8 @@ pack_stencil_cfg(struct v3dv_pipeline *pipeline,
*/
bool needs_front_and_back = false;
if ((any_dynamic_stencil_states) ||
memcmp(&ds_info->front, &ds_info->back, sizeof(ds_info->front))) {
memcmp(&state->ds->stencil.front, &state->ds->stencil.back,
sizeof(state->ds->stencil.front))) {
needs_front_and_back = true;
}
@ -342,35 +325,24 @@ pack_stencil_cfg(struct v3dv_pipeline *pipeline,
pipeline->emit_stencil_cfg[0] = true;
if (!needs_front_and_back) {
pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[0],
true, true, &ds_info->front, state);
true, true, &state->ds->stencil.front);
} else {
pipeline->emit_stencil_cfg[1] = true;
pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[0],
true, false, &ds_info->front, state);
true, false, &state->ds->stencil.front);
pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[1],
false, true, &ds_info->back, state);
false, true, &state->ds->stencil.back);
}
}
/* FIXME: Now that we are passing the vk_graphics_pipeline_state we could
* avoid passing all those parameters. But doing that we would need to change
* all the code that uses the VkXXX structures, and use instead the equivalent
* vk_xxx
*/
void
v3dX(pipeline_pack_state)(struct v3dv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *cb_info,
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const VkPipelineRasterizationStateCreateInfo *rs_info,
const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info,
const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info,
const VkPipelineMultisampleStateCreateInfo *ms_info,
const struct vk_graphics_pipeline_state *state)
{
pack_blend(pipeline, cb_info);
pack_cfg_bits(pipeline, ds_info, rs_info, pv_info, ls_info, ms_info);
pack_stencil_cfg(pipeline, ds_info, state);
pack_blend(pipeline, state->cb);
pack_cfg_bits(pipeline, state->rs, state->ms);
pack_stencil_cfg(pipeline, state);
}
static void

6
src/broadcom/vulkan/v3dvx_private.h
View file

@ -280,12 +280,6 @@ v3dX(meta_framebuffer_init)(struct v3dv_meta_framebuffer *fb,
/* Used at v3dv_pipeline */
void
v3dX(pipeline_pack_state)(struct v3dv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *cb_info,
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const VkPipelineRasterizationStateCreateInfo *rs_info,
const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info,
const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info,
const VkPipelineMultisampleStateCreateInfo *ms_info,
const struct vk_graphics_pipeline_state *state);
void
v3dX(pipeline_pack_compile_state)(struct v3dv_pipeline *pipeline,