diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 9fb80b89d5b..8e4c7af4d95 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1390,10 +1390,8 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, STATIC_ASSERT(AMDGPU_HW_IP_VCN_JPEG == AMD_IP_VCN_JPEG); STATIC_ASSERT(AMDGPU_HW_IP_VPE == AMD_IP_VPE); - if (!handle_env_var_force_family(info)) { - fprintf(stderr, "amdgpu: handle_env_var_force_family failed.\n"); + if (!handle_env_var_force_family(info)) return AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW; - } info->pci.valid = ac_drm_query_pci_bus_info(dev, info) == 0; if (require_pci_bus_info && !info->pci.valid) { diff --git a/src/amd/common/ac_surface_meta_address_test.c b/src/amd/common/ac_surface_meta_address_test.c index 11e20b0af86..4d8eafa3683 100644 --- a/src/amd/common/ac_surface_meta_address_test.c +++ b/src/amd/common/ac_surface_meta_address_test.c @@ -711,37 +711,37 @@ int main(int argc, char **argv) puts("Specify --full to run the full test."); puts("DCC:"); - for (unsigned i = 0; i < ARRAY_SIZE(ac_fake_hw_db); ++i) { + for (unsigned i = 0; i < ARRAY_SIZE(ac_surface_fake_devices); ++i) { struct radeon_info info = { .drm_major = 0 }; - get_radeon_info(&info, &ac_fake_hw_db[i]); + get_radeon_info(&info, &ac_surface_fake_devices[i]); if (info.gfx_level < GFX9 || info.gfx_level >= GFX12) continue; - run_dcc_address_test(ac_fake_hw_db[i].name, &info, full); + run_dcc_address_test(ac_surface_fake_devices[i].name, &info, full); } puts("HTILE:"); - for (unsigned i = 0; i < ARRAY_SIZE(ac_fake_hw_db); ++i) { + for (unsigned i = 0; i < ARRAY_SIZE(ac_surface_fake_devices); ++i) { struct radeon_info info = { .drm_major = 0 }; - get_radeon_info(&info, &ac_fake_hw_db[i]); + get_radeon_info(&info, &ac_surface_fake_devices[i]); /* Only GFX10+ is currently supported. GFX12 doesn't have HTILE. */ if (info.gfx_level < GFX10 || info.gfx_level >= GFX12) continue; - run_htile_address_test(ac_fake_hw_db[i].name, &info, full); + run_htile_address_test(ac_surface_fake_devices[i].name, &info, full); } puts("CMASK:"); - for (unsigned i = 0; i < ARRAY_SIZE(ac_fake_hw_db); ++i) { + for (unsigned i = 0; i < ARRAY_SIZE(ac_surface_fake_devices); ++i) { struct radeon_info info = { .drm_major = 0 }; - get_radeon_info(&info, &ac_fake_hw_db[i]); + get_radeon_info(&info, &ac_surface_fake_devices[i]); if (info.gfx_level >= GFX11) continue; - run_cmask_address_test(ac_fake_hw_db[i].name, &info, full); + run_cmask_address_test(ac_surface_fake_devices[i].name, &info, full); } return 0; diff --git a/src/amd/common/ac_surface_modifier_test.c b/src/amd/common/ac_surface_modifier_test.c index 6cac2068480..e9dd6867e5d 100644 --- a/src/amd/common/ac_surface_modifier_test.c +++ b/src/amd/common/ac_surface_modifier_test.c @@ -512,12 +512,12 @@ int main() struct u_vector test_entries; u_vector_init_pow2(&test_entries, 64, sizeof(struct test_entry)); - for (unsigned i = 0; i < ARRAY_SIZE(ac_fake_hw_db); ++i) { + for (unsigned i = 0; i < ARRAY_SIZE(ac_surface_fake_devices); ++i) { struct radeon_info info = { .drm_major = 0 }; - get_radeon_info(&info, &ac_fake_hw_db[i]); + get_radeon_info(&info, &ac_surface_fake_devices[i]); - run_modifier_test(&test_entries, ac_fake_hw_db[i].name, &info); + run_modifier_test(&test_entries, ac_surface_fake_devices[i].name, &info); } qsort(u_vector_tail(&test_entries), diff --git a/src/amd/common/ac_surface_test.h b/src/amd/common/ac_surface_test.h index 2bebc95454b..7f9bea21745 100644 --- a/src/amd/common/ac_surface_test.h +++ b/src/amd/common/ac_surface_test.h @@ -12,287 +12,90 @@ #include "amdgfxregs.h" #include "addrlib/src/amdgpu_asic_addr.h" -#ifdef _WIN32 -#define AMDGPU_FAMILY_VI 130 -#define AMDGPU_FAMILY_AI 141 -#define AMDGPU_FAMILY_RV 142 -#define AMDGPU_FAMILY_NV 143 -#else -#include "drm-uapi/amdgpu_drm.h" -#endif +#include "amdgpu_devices.h" +#include "ac_linux_drm.h" -typedef void (*gpu_init_func)(struct radeon_info *info); - -static void init_polaris12(struct radeon_info *info) -{ - info->family = CHIP_POLARIS12; - info->gfx_level = GFX8; - info->family_id = AMDGPU_FAMILY_VI; - info->chip_external_rev = 0x64; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 64; - info->max_render_backends = 4; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 256; - - uint32_t si_tile_mode_array[] = { - 0x00800150, 0x00800950, 0x00801150, 0x00801950, 0x00802950, - 0x00802948, 0x00802954, 0x00802954, 0x00000144, 0x02000148, - 0x02000150, 0x06000154, 0x06000154, 0x02400148, 0x02400150, - 0x02400170, 0x06400154, 0x06400154, 0x0040014c, 0x0100014c, - 0x0100015c, 0x01000174, 0x01000164, 0x01000164, 0x0040015c, - 0x01000160, 0x01000178, 0x02c00148, 0x02c00150, 0x06c00154, - 0x06c00154, 0x00000000 - }; - memcpy(info->si_tile_mode_array, si_tile_mode_array, sizeof(si_tile_mode_array)); - info->gb_addr_config = 0x22011002; -} - -static void init_vega10(struct radeon_info *info) -{ - info->family = CHIP_VEGA10; - info->gfx_level = GFX9; - info->family_id = AMDGPU_FAMILY_AI; - info->chip_external_rev = 0x01; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 64; - info->max_render_backends = 16; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 256; - - info->gb_addr_config = 0x2a114042; -} - -static void init_vega20(struct radeon_info *info) -{ - info->family = CHIP_VEGA20; - info->gfx_level = GFX9; - info->family_id = AMDGPU_FAMILY_AI; - info->chip_external_rev = 0x30; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 64; - info->max_render_backends = 16; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 256; - - info->gb_addr_config = 0x2a114042; -} - - -static void init_raven(struct radeon_info *info) -{ - info->family = CHIP_RAVEN; - info->gfx_level = GFX9; - info->family_id = AMDGPU_FAMILY_RV; - info->chip_external_rev = 0x01; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 64; - info->max_render_backends = 2; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 256; - - info->gb_addr_config = 0x24000042; -} - -static void init_raven2(struct radeon_info *info) -{ - info->family = CHIP_RAVEN2; - info->gfx_level = GFX9; - info->family_id = AMDGPU_FAMILY_RV; - info->chip_external_rev = 0x82; - info->use_display_dcc_unaligned = true; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 64; - info->max_render_backends = 1; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 256; - - info->gb_addr_config = 0x26013041; -} - -static void init_navi10(struct radeon_info *info) -{ - info->family = CHIP_NAVI10; - info->gfx_level = GFX10; - info->family_id = AMDGPU_FAMILY_NV; - info->chip_external_rev = 3; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 512; - - info->gb_addr_config = 0x00100044; -} - -static void init_navi14(struct radeon_info *info) -{ - info->family = CHIP_NAVI14; - info->gfx_level = GFX10; - info->family_id = AMDGPU_FAMILY_NV; - info->chip_external_rev = 0x15; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = false; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 512; - - info->gb_addr_config = 0x00000043; -} - -static void init_gfx103(struct radeon_info *info) -{ - info->family = CHIP_NAVI21; /* This doesn't affect tests. */ - info->gfx_level = GFX10_3; - info->family_id = AMDGPU_FAMILY_NV; - info->chip_external_rev = 0x28; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 512; - - info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */ -} - -static void init_navi31(struct radeon_info *info) -{ - info->family = CHIP_NAVI31; - info->gfx_level = GFX11; - info->family_id = FAMILY_NV3; - info->chip_external_rev = 0x01; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 768; - - info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */ -} - -static void init_navi32(struct radeon_info *info) -{ - info->family = CHIP_NAVI32; - info->gfx_level = GFX11; - info->family_id = FAMILY_NV3; - info->chip_external_rev = 0x20; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 768; - - info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */ -} - -static void init_navi33(struct radeon_info *info) -{ - info->family = CHIP_NAVI33; - info->gfx_level = GFX11; - info->family_id = FAMILY_NV3; - info->chip_external_rev = 0x10; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 512; - - info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */ -} - -static void init_gfx11_apu(struct radeon_info *info) -{ - info->family = CHIP_PHOENIX; - info->gfx_level = GFX11; - info->family_id = FAMILY_PHX; - info->chip_external_rev = 0x01; - info->use_display_dcc_unaligned = false; - info->use_display_dcc_with_retile_blit = true; - info->has_graphics = true; - info->tcc_cache_line_size = 128; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 512; - - info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */ -} - -static void init_gfx12(struct radeon_info *info) -{ - info->family = CHIP_GFX1200; - info->gfx_level = GFX12; - info->family_id = FAMILY_NV4; - info->chip_external_rev = 0x01; - info->has_graphics = true; - info->tcc_cache_line_size = 256; - info->has_rbplus = true; - info->rbplus_allowed = true; - info->compiler_info.num_physical_wave64_vgprs_per_simd = 768; - - info->gb_addr_config = 0; /* Other fields are set by test cases. */ -} - -struct ac_fake_hw { +struct ac_surface_fake_device { const char *name; - gpu_init_func init; + const char *device_name; int banks_or_pkrs; int pipes; int se; int rb_per_se; }; -static struct ac_fake_hw ac_fake_hw_db[] = { - {"polaris12", init_polaris12}, - {"vega10", init_vega10, 4, 2, 2, 2}, - {"vega10_diff_bank", init_vega10, 3, 2, 2, 2}, - {"vega10_diff_rb", init_vega10, 4, 2, 2, 0}, - {"vega10_diff_pipe", init_vega10, 4, 0, 2, 2}, - {"vega10_diff_se", init_vega10, 4, 2, 1, 2}, - {"vega20", init_vega20, 4, 2, 2, 2}, - {"raven", init_raven, 0, 2, 0, 1}, - {"raven2", init_raven2, 3, 1, 0, 1}, +static struct ac_surface_fake_device ac_surface_fake_devices[] = { + {"polaris12", "polaris12"}, + {"vega10", "vega10", 4, 2, 2, 2}, + {"vega10_diff_bank", "vega10", 3, 2, 2, 2}, + {"vega10_diff_rb", "vega10", 4, 2, 2, 0}, + {"vega10_diff_pipe", "vega10", 4, 0, 2, 2}, + {"vega10_diff_se", "vega10", 4, 2, 1, 2}, + {"vega20", "vega20", 4, 2, 2, 2}, + {"raven", "raven", 0, 2, 0, 1}, + {"raven2", "raven2", 3, 1, 0, 1}, /* Just test a bunch of different numbers. (packers, pipes) */ - {"navi10", init_navi10, 0, 4}, - {"navi10_diff_pipe", init_navi10, 0, 3}, - {"navi10_diff_pkr", init_navi10, 1, 4}, - {"navi14", init_navi14, 1, 3}, - {"navi21", init_gfx103, 4, 4}, - {"navi21_8pkr", init_gfx103, 3, 4}, - {"navi22", init_gfx103, 3, 3}, - {"navi24", init_gfx103, 2, 2}, - {"vangogh", init_gfx103, 1, 2}, - {"vangogh_1pkr", init_gfx103, 0, 2}, - {"raphael", init_gfx103, 0, 1}, - {"navi31", init_navi31, 5, 5}, - {"navi32", init_navi32, 4, 4}, - {"navi33", init_navi33, 3, 3}, - {"phoenix", init_gfx11_apu, 2, 2}, - {"phoenix_2pkr", init_gfx11_apu, 1, 2}, - {"phoenix2", init_gfx11_apu, 0, 2}, - {"phoenix2_2pipe", init_gfx11_apu, 0, 1}, - {"gfx12", init_gfx12, 4, 4}, + {"navi10", "navi10", 0, 4}, + {"navi10_diff_pipe", "navi10", 0, 3}, + {"navi10_diff_pkr", "navi10", 1, 4}, + {"navi21", "navi21", 4, 4}, + {"navi21_8pkr", "navi21", 3, 4}, + {"navi22", "navi21", 3, 3}, + {"navi24", "navi21", 2, 2}, + {"vangogh", "vangogh", 1, 2}, + {"vangogh_1pkr", "vangogh", 0, 2}, + {"raphael", "vangogh", 0, 1}, + {"navi31", "navi31", 5, 5}, + {"navi33", "navi33", 3, 3}, + {"phoenix", "phoenix", 2, 2}, + {"phoenix_2pkr", "phoenix", 1, 2}, + {"phoenix2", "phoenix", 0, 2}, + {"phoenix2_2pipe", "phoenix", 0, 1}, + {"gfx12", "gfx1201", 4, 4}, }; -static void get_radeon_info(struct radeon_info *info, struct ac_fake_hw *hw) +static const struct amdgpu_device *find_amdgpu_device(const char *name) { - if (info->drm_major != 3) { - info->drm_major = 3; - info->drm_minor = 30; + for (int i = 0;i < num_amdgpu_devices; i++) { + if (strcmp(amdgpu_devices[i].name, name) == 0) + return &amdgpu_devices[i]; } + assert(false); + return NULL; +} - hw->init(info); +static void get_radeon_info(struct radeon_info *info, const struct ac_surface_fake_device *hw) +{ + const struct amdgpu_device *dev = find_amdgpu_device(hw->device_name); + struct amdgpu_gpu_info gpu_info = { 0 }; + + /* Emulate ac_drm_read_mm_registers to read relevant fields. */ + gpu_info.gb_addr_cfg = dev->mmr_regs[2]; + if (dev->dev.family < AMDGPU_FAMILY_AI) { + for (int i = 0; i < 32; i++) { + for (int j = 0; j < dev->mmr_reg_count; j++) { + const uint32_t *triple = &dev->mmr_regs[j * 3]; + + if (triple[0] == 0x2644 + i) + gpu_info.gb_tile_mode[i] = triple[2]; + } + } + } + info->kernel_has_modifiers = 1; + + ac_fill_hw_ip_info(info, &dev->dev, AMD_IP_GFX, &dev->hw_ip_gfx); + ac_fill_hw_ip_info(info, &dev->dev, AMD_IP_COMPUTE, &dev->hw_ip_compute); + + ac_identify_chip(info, &dev->dev); + + ac_fill_memory_info(info, &dev->dev, &dev->mem); + ac_fill_hw_info(info, &dev->dev); + + ac_fill_tiling_info(info, &gpu_info); + ac_fill_feature_info(info, &dev->dev); + ac_fill_bug_info(info); + ac_fill_tess_info(info); + ac_fill_compiler_info(info, &dev->dev); switch(info->gfx_level) { case GFX9: diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/common/amdgpu_devices.c similarity index 100% rename from src/amd/drm-shim/amdgpu_devices.c rename to src/amd/common/amdgpu_devices.c diff --git a/src/amd/drm-shim/amdgpu_devices.h b/src/amd/common/amdgpu_devices.h similarity index 100% rename from src/amd/drm-shim/amdgpu_devices.h rename to src/amd/common/amdgpu_devices.h diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build index 76c747d52ea..fd143817e0a 100644 --- a/src/amd/common/meson.build +++ b/src/amd/common/meson.build @@ -242,7 +242,7 @@ if with_tests and not with_platform_windows 'ac_surface_modifier_test', executable( 'ac_surface_modifier_test', - ['ac_surface_modifier_test.c'], + ['ac_surface_modifier_test.c', 'amdgpu_devices.c'], link_with: [libamd_common, libamdgpu_addrlib], include_directories : [ inc_amd, inc_include, inc_src, @@ -259,7 +259,7 @@ if with_tests and not with_platform_windows 'ac_surface_meta_address_test', executable( 'ac_surface_meta_address_test', - ['ac_surface_meta_address_test.c'], + ['ac_surface_meta_address_test.c', 'amdgpu_devices.c'], link_with: [libamd_common, libamdgpu_addrlib], include_directories : [ inc_amd, inc_include, inc_src, diff --git a/src/amd/drm-shim/amdgpu_noop_drm_shim.c b/src/amd/drm-shim/amdgpu_noop_drm_shim.c index eea72e819ea..1ac8a396e46 100644 --- a/src/amd/drm-shim/amdgpu_noop_drm_shim.c +++ b/src/amd/drm-shim/amdgpu_noop_drm_shim.c @@ -6,7 +6,7 @@ #include #include #include -#include "amdgpu_devices.h" +#include "common/amdgpu_devices.h" #include "common/amd_family.h" #include "drm-shim/amdgpu_noop_drm_shim.h" #include "drm-shim/drm_shim.h" diff --git a/src/amd/drm-shim/meson.build b/src/amd/drm-shim/meson.build index c324846501d..73e0e1ff571 100644 --- a/src/amd/drm-shim/meson.build +++ b/src/amd/drm-shim/meson.build @@ -12,7 +12,7 @@ libradeon_noop_drm_shim = shared_library( libamdgpu_noop_drm_shim = shared_library( 'amdgpu_noop_drm_shim', - ['amdgpu_noop_drm_shim.c', 'amdgpu_devices.c'], + ['amdgpu_noop_drm_shim.c', '../common/amdgpu_devices.c'], include_directories: [inc_include, inc_src, inc_amd], dependencies: dep_drm_shim, install : true,