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tu: Use proper reg packing in another place.

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
This commit is contained in:
Emma Anholt 2025-12-02 17:46:59 -08:00 • committed by Marge Bot
parent dae582ecc1
commit 7e027d5672
2 changed files with 4 additions and 5 deletions
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5
src/freedreno/vulkan/tu_clear_blit.cc
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@ -1657,8 +1657,7 @@ r3d_setup(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, GRAS_VRS_CONFIG(CHIP));
}
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
tu_cs_emit_regs(cs, GRAS_SC_CNTL(CHIP, .ccusinglecachelinesize = 2));
/* Disable sample counting in order to not affect occlusion query. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.disable = true));
@ -4211,7 +4210,7 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_WRITE_MASK(.wrmask = 0xff));
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL(.ref = s_clear_val));
tu_cs_emit_regs(cs, A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2));
tu_cs_emit_regs(cs, GRAS_SC_CNTL(CHIP, .ccusinglecachelinesize = 2));
unsigned num_rts = util_bitcount(clear_rts);
uint32_t packed_clear_value[MAX_RTS][4];

4
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -3581,8 +3581,8 @@ tu6_emit_prim_mode_sysmem(struct tu_cs *cs,
if (sysmem_prim_mode == FLUSH_PER_OVERLAP_AND_OVERWRITE)
*sysmem_single_prim_mode = true;
tu_cs_emit_regs(cs, A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2,
.single_prim_mode = sysmem_prim_mode));
tu_cs_emit_regs(cs, GRAS_SC_CNTL(CHIP, .ccusinglecachelinesize = 2,
.single_prim_mode = sysmem_prim_mode));
}
static const enum mesa_vk_dynamic_graphics_state tu_fragment_shading_rate_state[] = {