From 7da1e4c326d9f3213060c45ddeb1c65afcba7bff Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 30 Jun 2023 16:05:58 -0400 Subject: [PATCH] pan/mdg: Fix 2-const CSEL at block beginning mir_prev_op will point to the last instruction of the block in that case because the block instruction list is circular. That would cause an invald write-after-read relationship between the move we insert with the constants and the CSEL reading them, which DCE "helpfully" optimizes out, leaving a read from an undefined def. That ends up getting RA'd to an invalid register. All in all, pretty bad. Identified due to a new assert fail after the proper temp_count fix. Affects dEQP-GLES31.functional.separate_shader.random.12. No shader-db changes. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Italo Nicola Part-of: --- src/panfrost/midgard/midgard_compile.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 78ea00d66b2..32b7ec0eac1 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -2471,8 +2471,17 @@ inline_alu_constants(compiler_context *ctx, midgard_block *block) /* Set the source */ alu->src[1] = scratch; - /* Inject us -before- the last instruction which set r31 */ - mir_insert_instruction_before(ctx, mir_prev_op(alu), ins); + /* Inject us -before- the last instruction which set r31, if + * possible. + */ + midgard_instruction *first = list_first_entry( + &block->base.instructions, midgard_instruction, link); + + if (alu == first) { + mir_insert_instruction_before(ctx, alu, ins); + } else { + mir_insert_instruction_before(ctx, mir_prev_op(alu), ins); + } } } }