From 7d73389a95134874e2713f39242356a5db510915 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 18 Aug 2025 14:15:53 +0200 Subject: [PATCH] radv: add missing L2 invalidate cache flush for non-coherent images Images aren't always coherent with L2 and AMD generations have different rules, see radv_image_is_l2_coherent() for the full picture. This fixes a rendering issue on GFX9 because depth/stencil images aren't coherent, but this also affects color images. This also fixes a cache coherency issue with an ongoing extension. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12274 Signed-off-by: Samuel Pitoiset Part-of: (cherry picked from commit 99b287bde583906280e721569ddfa46c71060314) --- .pick_status.json | 2 +- src/amd/vulkan/radv_cmd_buffer.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index 5bb65a87558..0d64198f81f 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -5194,7 +5194,7 @@ "description": "radv: add missing L2 invalidate cache flush for non-coherent images", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index dc15ecd3ffc..91cbf18c12d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6568,12 +6568,16 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 if (src_flags & VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT) { flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; + if (!image_is_coherent) + flush_bits |= RADV_CMD_FLAG_INV_L2; if (has_CB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; } if (src_flags & VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT) { flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; + if (!image_is_coherent) + flush_bits |= RADV_CMD_FLAG_INV_L2; if (has_DB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; }