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https://gitlab.freedesktop.org/mesa/mesa.git
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intel: Remove unused intel/server files
This commit is contained in:
Kristian Høgsberg
parent
2b3b76a4a0
commit
7d349f588a
5 changed files with 2 additions and 397 deletions
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@ -56,7 +56,7 @@ C_SOURCES = \
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ASM_SOURCES =
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DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
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DRIVER_DEFINES = -I../intel -DI915 \
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$(shell pkg-config libdrm --atleast-version=2.3.1 \
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&& echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP")
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@ -106,7 +106,7 @@ C_SOURCES = \
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ASM_SOURCES =
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DRIVER_DEFINES = -I../intel -I../intel/server
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DRIVER_DEFINES = -I../intel
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INCLUDES += $(INTEL_CFLAGS)
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DRI_LIB_DEPS += $(INTEL_LIBS)
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@ -39,8 +39,6 @@
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#include "drivers/common/driverfuncs.h"
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#include "drivers/common/meta.h"
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#include "i830_dri.h"
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#include "intel_chipset.h"
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#include "intel_buffers.h"
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#include "intel_tex.h"
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@ -1,62 +0,0 @@
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i830_dri.h,v 1.6 2003/09/28 20:15:59 alanh Exp $ */
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#ifndef _I830_DRI_H
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#define _I830_DRI_H
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#include "xf86drm.h"
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#define I830_MAX_DRAWABLES 256
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#define I830_MAJOR_VERSION 1
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#define I830_MINOR_VERSION 9
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#define I830_PATCHLEVEL 0
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#define I830_REG_SIZE 0x80000
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typedef struct _I830DRIRec {
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drm_handle_t regs;
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drmSize regsSize;
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drmSize unused1; /* backbufferSize */
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drm_handle_t unused2; /* backbuffer */
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drmSize unused3; /* depthbufferSize */
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drm_handle_t unused4; /* depthbuffer */
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drmSize unused5; /* rotatedSize */
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drm_handle_t unused6; /* rotatedbuffer */
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drm_handle_t unused7; /* textures */
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int unused8; /* textureSize */
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drm_handle_t unused9; /* agp_buffers */
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drmSize unused10; /* agp_buf_size */
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int deviceID;
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int width;
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int height;
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int mem;
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int cpp;
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int bitsPerPixel;
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int unused11[8]; /* was front/back/depth/rotated offset/pitch */
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int unused12; /* logTextureGranularity */
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int unused13; /* textureOffset */
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int irq;
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int sarea_priv_offset;
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} I830DRIRec, *I830DRIPtr;
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typedef struct {
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/* Nothing here yet */
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int dummy;
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} I830ConfigPrivRec, *I830ConfigPrivPtr;
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typedef struct {
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/* Nothing here yet */
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int dummy;
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} I830DRIContextRec, *I830DRIContextPtr;
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#endif
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@ -1,331 +0,0 @@
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#ifndef _INTEL_H_
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#define _INTEL_H_
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#include "xf86drm.h" /* drm_handle_t, etc */
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/* Intel */
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#ifndef PCI_CHIP_I810
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I810_BRIDGE 0x7120
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#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
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#define PCI_CHIP_I810_E_BRIDGE 0x7124
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#define PCI_CHIP_I815_BRIDGE 0x1130
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#endif
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I830_M 0x3577
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#ifndef PCI_CHIP_I855_GM
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I855_GM_BRIDGE 0x3580
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#endif
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#ifndef PCI_CHIP_I865_G
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I865_G_BRIDGE 0x2570
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#endif
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#ifndef PCI_CHIP_I915_G
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_I915_G_BRIDGE 0x2580
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#endif
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#ifndef PCI_CHIP_I915_GM
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_I915_GM_BRIDGE 0x2590
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#endif
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#ifndef PCI_CHIP_E7221_G
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#define PCI_CHIP_E7221_G 0x258A
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/* Same as I915_G_BRIDGE */
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#define PCI_CHIP_E7221_G_BRIDGE 0x2580
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#endif
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#ifndef PCI_CHIP_I945_G
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_G_BRIDGE 0x2770
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#endif
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#ifndef PCI_CHIP_I945_GM
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
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#endif
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#define IS_I810(pI810) (pI810->Chipset == PCI_CHIP_I810 || \
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pI810->Chipset == PCI_CHIP_I810_DC100 || \
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pI810->Chipset == PCI_CHIP_I810_E)
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#define IS_I815(pI810) (pI810->Chipset == PCI_CHIP_I815)
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#define IS_I830(pI810) (pI810->Chipset == PCI_CHIP_I830_M)
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#define IS_845G(pI810) (pI810->Chipset == PCI_CHIP_845_G)
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#define IS_I85X(pI810) (pI810->Chipset == PCI_CHIP_I855_GM)
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#define IS_I852(pI810) (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
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#define IS_I855(pI810) (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
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#define IS_I865G(pI810) (pI810->Chipset == PCI_CHIP_I865_G)
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#define IS_I915G(pI810) (pI810->Chipset == PCI_CHIP_I915_G || pI810->Chipset == PCI_CHIP_E7221_G)
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#define IS_I915GM(pI810) (pI810->Chipset == PCI_CHIP_I915_GM)
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#define IS_I945G(pI810) (pI810->Chipset == PCI_CHIP_I945_G)
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#define IS_I945GM(pI810) (pI810->Chipset == PCI_CHIP_I945_GM)
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#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810))
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#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_MEM_MASK 0x1
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#define I830_GMCH_MEM_64M 0x1
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#define I830_GMCH_MEM_128M 0
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_DISABLED 0x00
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I855_GMCH_GMS_MASK (0x7 << 4)
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#define I855_GMCH_GMS_DISABLED 0x00
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
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typedef unsigned char Bool;
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#define TRUE 1
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#define FALSE 0
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#define PIPE_NONE 0<<0
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#define PIPE_CRT 1<<0
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#define PIPE_TV 1<<1
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#define PIPE_DFP 1<<2
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#define PIPE_LFP 1<<3
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#define PIPE_CRT2 1<<4
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#define PIPE_TV2 1<<5
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#define PIPE_DFP2 1<<6
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#define PIPE_LFP2 1<<7
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typedef struct _I830MemPool *I830MemPoolPtr;
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typedef struct _I830MemRange *I830MemRangePtr;
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typedef struct _I830MemRange {
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long Start;
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long End;
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long Size;
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unsigned long Physical;
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unsigned long Offset; /* Offset of AGP-allocated portion */
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unsigned long Alignment;
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drm_handle_t Key;
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unsigned long Pitch; // add pitch
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I830MemPoolPtr Pool;
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} I830MemRange;
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typedef struct _I830MemPool {
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I830MemRange Total;
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I830MemRange Free;
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I830MemRange Fixed;
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I830MemRange Allocated;
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} I830MemPool;
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typedef struct {
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int tail_mask;
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I830MemRange mem;
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unsigned char *virtual_start;
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int head;
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int tail;
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int space;
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} I830RingBuffer;
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typedef struct _I830Rec {
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unsigned char *MMIOBase;
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unsigned char *FbBase;
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int cpp;
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uint32_t aper_size;
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unsigned int bios_version;
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/* These are set in PreInit and never changed. */
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long FbMapSize;
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long TotalVideoRam;
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I830MemRange StolenMemory; /* pre-allocated memory */
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long BIOSMemorySize; /* min stolen pool size */
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int BIOSMemSizeLoc;
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/* These change according to what has been allocated. */
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long FreeMemory;
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I830MemRange MemoryAperture;
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I830MemPool StolenPool;
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long allocatedMemory;
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/* Regions allocated either from the above pools, or from agpgart. */
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/* for single and dual head configurations */
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I830MemRange FrontBuffer;
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I830MemRange FrontBuffer2;
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I830MemRange Scratch;
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I830MemRange Scratch2;
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I830RingBuffer *LpRing;
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I830MemRange BackBuffer;
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I830MemRange DepthBuffer;
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I830MemRange TexMem;
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int TexGranularity;
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I830MemRange ContextMem;
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int drmMinor;
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Bool have3DWindows;
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Bool NeedRingBufferLow;
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Bool allowPageFlip;
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Bool disableTiling;
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int Chipset;
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unsigned long LinearAddr;
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unsigned long MMIOAddr;
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drmSize registerSize; /**< \brief MMIO register map size */
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drm_handle_t registerHandle; /**< \brief MMIO register map handle */
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// IOADDRESS ioBase;
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int irq; /**< \brief IRQ number */
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int GttBound;
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drm_handle_t ring_map;
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unsigned int Fence[8];
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} I830Rec;
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/*
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* 12288 is set as the maximum, chosen because it is enough for
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* 1920x1440@32bpp with a 2048 pixel line pitch with some to spare.
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*/
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#define I830_MAXIMUM_VBIOS_MEM 12288
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#define I830_DEFAULT_VIDEOMEM_2D (MB(32) / 1024)
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#define I830_DEFAULT_VIDEOMEM_3D (MB(64) / 1024)
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/* Flags for memory allocation function */
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#define FROM_ANYWHERE 0x00000000
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#define FROM_POOL_ONLY 0x00000001
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#define FROM_NEW_ONLY 0x00000002
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#define FROM_MASK 0x0000000f
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#define ALLOCATE_AT_TOP 0x00000010
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#define ALLOCATE_AT_BOTTOM 0x00000020
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#define FORCE_GAPS 0x00000040
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#define NEED_PHYSICAL_ADDR 0x00000100
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#define ALIGN_BOTH_ENDS 0x00000200
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#define FORCE_LOW 0x00000400
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#define ALLOC_NO_TILING 0x00001000
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#define ALLOC_INITIAL 0x00002000
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#define ALLOCATE_DRY_RUN 0x80000000
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/* Chipset registers for VIDEO BIOS memory RW access */
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#define _855_DRAM_RW_CONTROL 0x58
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#define _845_DRAM_RW_CONTROL 0x90
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#define DRAM_WRITE 0x33330000
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#define KB(x) ((x) * 1024)
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#define MB(x) ((x) * KB(1024))
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#define GTT_PAGE_SIZE KB(4)
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#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
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#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
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#define ROUND_TO_PAGE(x) ROUND_TO((x), GTT_PAGE_SIZE)
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#define ROUND_TO_MB(x) ROUND_TO((x), MB(1))
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#define PRIMARY_RINGBUFFER_SIZE KB(128)
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/* Ring buffer registers, p277, overview p19
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*/
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#define LP_RING 0x2030
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#define HP_RING 0x2040
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#define RING_TAIL 0x00
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#define TAIL_ADDR 0x000FFFF8
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#define I830_TAIL_MASK 0x001FFFF8
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#define RING_HEAD 0x04
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#define HEAD_WRAP_COUNT 0xFFE00000
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#define HEAD_WRAP_ONE 0x00200000
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#define HEAD_ADDR 0x001FFFFC
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#define I830_HEAD_MASK 0x001FFFFC
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#define RING_START 0x08
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#define START_ADDR 0x03FFFFF8
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#define I830_RING_START_MASK 0xFFFFF000
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#define RING_LEN 0x0C
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#define RING_NR_PAGES 0x001FF000
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#define I830_RING_NR_PAGES 0x001FF000
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#define RING_REPORT_MASK 0x00000006
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#define RING_REPORT_64K 0x00000002
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#define RING_REPORT_128K 0x00000004
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#define RING_NO_REPORT 0x00000000
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#define RING_VALID_MASK 0x00000001
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#define RING_VALID 0x00000001
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#define RING_INVALID 0x00000000
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/* Fence/Tiling ranges [0..7]
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*/
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#define FENCE 0x2000
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#define FENCE_NR 8
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#define I915G_FENCE_START_MASK 0x0ff00000
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#define I830_FENCE_START_MASK 0x07f80000
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#define FENCE_START_MASK 0x03F80000
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#define FENCE_X_MAJOR 0x00000000
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#define FENCE_Y_MAJOR 0x00001000
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#define FENCE_SIZE_MASK 0x00000700
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#define FENCE_SIZE_512K 0x00000000
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#define FENCE_SIZE_1M 0x00000100
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#define FENCE_SIZE_2M 0x00000200
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#define FENCE_SIZE_4M 0x00000300
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#define FENCE_SIZE_8M 0x00000400
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#define FENCE_SIZE_16M 0x00000500
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#define FENCE_SIZE_32M 0x00000600
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#define FENCE_SIZE_64M 0x00000700
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#define I915G_FENCE_SIZE_1M 0x00000000
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#define I915G_FENCE_SIZE_2M 0x00000100
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#define I915G_FENCE_SIZE_4M 0x00000200
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#define I915G_FENCE_SIZE_8M 0x00000300
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#define I915G_FENCE_SIZE_16M 0x00000400
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#define I915G_FENCE_SIZE_32M 0x00000500
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#define I915G_FENCE_SIZE_64M 0x00000600
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#define I915G_FENCE_SIZE_128M 0x00000700
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#define FENCE_PITCH_1 0x00000000
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#define FENCE_PITCH_2 0x00000010
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#define FENCE_PITCH_4 0x00000020
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#define FENCE_PITCH_8 0x00000030
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#define FENCE_PITCH_16 0x00000040
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#define FENCE_PITCH_32 0x00000050
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#define FENCE_PITCH_64 0x00000060
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#define FENCE_VALID 0x00000001
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#include <mmio.h>
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# define MMIO_IN8(base, offset) \
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*(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
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# define MMIO_IN32(base, offset) \
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read_MMIO_LE32(base, offset)
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# define MMIO_OUT8(base, offset, val) \
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*(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
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# define MMIO_OUT32(base, offset, val) \
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*(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
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/* Memory mapped register access macros */
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#define INREG8(addr) MMIO_IN8(MMIO, addr)
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#define INREG(addr) MMIO_IN32(MMIO, addr)
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#define OUTREG8(addr, val) MMIO_OUT8(MMIO, addr, val)
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#define OUTREG(addr, val) MMIO_OUT32(MMIO, addr, val)
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#define DSPABASE 0x70184
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#endif
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