fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 03:08:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

i965: don't treat swz differently and upload vertex buffers

Browse source
This commit is contained in:
Zack Rusin 2007-12-18 09:59:54 -05:00
parent e2a669aed4
commit 7cef9237ae
3 changed files with 24 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/mesa/pipe/i965simple/brw_draw.c
View file

@ -158,10 +158,13 @@ static boolean brw_try_draw_elements( struct pipe_context *pipe,
/* Upload index, vertex data:
*/
if (index_buffer &&
if (index_buffer &&
!brw_upload_indices( brw, index_buffer, index_size, start, count ))
return FALSE;
if (!brw_upload_vertex_buffers(brw))
return FALSE;
if (!brw_upload_vertex_elements( brw ))
return FALSE;

2
src/mesa/pipe/i965simple/brw_draw_upload.c
View file

@ -217,7 +217,7 @@ boolean brw_upload_vertex_buffers( struct brw_context *brw )
for (i = 0; i < BRW_VEP_MAX; i++)
{
if (brw->vb.vbo_array[i]->buffer == NULL) {
if (brw->vb.vbo_array[i] == NULL) {
nr_enabled = i;
break;
}

31
src/mesa/pipe/i965simple/brw_vs_emit.c
View file

@ -995,7 +995,7 @@ static void process_declaration(const struct tgsi_full_declaration *decl,
printf("DECLARATION MASK = %d\n",
decl->u.DeclarationMask.Mask);
assert(0);
} else { //range
} else { /*range*/
idx = decl->u.DeclarationRange.First;
}
switch (decl->Semantic.SemanticName) {
@ -1057,17 +1057,15 @@ static void process_instruction(struct brw_vs_compile *c,
unsigned insn, if_insn = 0;
*/
/* Get argument regs. SWZ is special and does this itself. */
if (inst->Instruction.Opcode != TGSI_OPCODE_SWZ)
for (i = 0; i < 3; i++) {
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
index = src->SrcRegister.Index;
file = src->SrcRegister.File;
if (file == TGSI_FILE_OUTPUT&&c->output_regs[index].used_in_src)
args[i] = c->output_regs[index].reg;
else
args[i] = get_arg(c, &src->SrcRegister);
}
for (i = 0; i < 3; i++) {
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
index = src->SrcRegister.Index;
file = src->SrcRegister.File;
if (file == TGSI_FILE_OUTPUT&&c->output_regs[index].used_in_src)
args[i] = c->output_regs[index].reg;
else
args[i] = get_arg(c, &src->SrcRegister);
}
/* Get dest regs. Note that it is possible for a reg to be both
* dst and arg, given the static allocation of registers. So
@ -1208,11 +1206,16 @@ static void process_instruction(struct brw_vs_compile *c,
break;
#endif
case TGSI_OPCODE_RET:
#if 0
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(-4));
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
#else
/*brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));*/
#endif
break;
case TGSI_OPCODE_END:
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
break;
@ -1295,7 +1298,11 @@ void brw_vs_emit(struct brw_vs_compile *c)
* now that we know what vars are being used allocate
* registers for them.*/
brw_vs_alloc_regs(c, &prog_info);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
brw_set_access_mode(p, BRW_ALIGN_16);
allocated_registers = 1;
}
process_instruction(c, inst, &prog_info);