From 7ce66e2b6122b64769a870bb73f8f0199bc2f524 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 2 Jan 2025 01:03:46 -0800 Subject: [PATCH] brw: Add a new MEMORY_MODE_CONSTANT option This will translate to HDC Constant Cache loads or LSC UGM loads. On LSC, MEMORY_MODE_UNTYPED would be fine, but for HDC we need to distinguish between the regular and constant cache data ports. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_eu_defines.h | 1 + src/intel/compiler/brw_fs_nir.cpp | 5 ++++- src/intel/compiler/brw_lower_logical_sends.cpp | 6 ++++++ src/intel/compiler/brw_print.cpp | 1 + 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 759dc3f67a4..03293fb01a0 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -643,6 +643,7 @@ enum memory_logical_mode { MEMORY_MODE_UNTYPED, MEMORY_MODE_SHARED_LOCAL, MEMORY_MODE_SCRATCH, + MEMORY_MODE_CONSTANT, }; enum memory_logical_srcs { diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 0b86de51e1c..c0cd3fea493 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6912,6 +6912,8 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, break; case nir_intrinsic_load_ubo_uniform_block_intel: + srcs[MEMORY_LOGICAL_MODE] = brw_imm_ud(MEMORY_MODE_CONSTANT); + FALLTHROUGH; case nir_intrinsic_load_ssbo: case nir_intrinsic_store_ssbo: case nir_intrinsic_ssbo_atomic: @@ -6919,7 +6921,8 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, case nir_intrinsic_load_ssbo_block_intel: case nir_intrinsic_store_ssbo_block_intel: case nir_intrinsic_load_ssbo_uniform_block_intel: - srcs[MEMORY_LOGICAL_MODE] = brw_imm_ud(MEMORY_MODE_UNTYPED); + if (srcs[MEMORY_LOGICAL_MODE].file == BAD_FILE) + srcs[MEMORY_LOGICAL_MODE] = brw_imm_ud(MEMORY_MODE_UNTYPED); srcs[MEMORY_LOGICAL_BINDING_TYPE] = brw_imm_ud(get_nir_src_bindless(ntb, instr->src[is_store ? 1 : 0]) ? LSC_ADDR_SURFTYPE_BSS : LSC_ADDR_SURFTYPE_BTI); diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index b249e176fa1..29e15907ec6 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -1531,6 +1531,7 @@ lower_lsc_memory_logical_send(const fs_builder &bld, fs_inst *inst) switch (mode) { case MEMORY_MODE_UNTYPED: + case MEMORY_MODE_CONSTANT: case MEMORY_MODE_SCRATCH: inst->sfid = GFX12_SFID_UGM; break; @@ -1780,6 +1781,11 @@ lower_hdc_memory_logical_send(const fs_builder &bld, fs_inst *inst) desc = brw_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group, components, !has_dest); } + } else if (mode == MEMORY_MODE_CONSTANT) { + assert(block); /* non-block loads not yet handled */ + + sfid = GFX6_SFID_DATAPORT_CONSTANT_CACHE; + desc = brw_dp_oword_block_rw_desc(devinfo, false, components, !has_dest); } else if (addr_size == LSC_ADDR_SIZE_A64) { assert(binding_type == LSC_ADDR_SURFTYPE_FLAT); assert(!dword_scattered); diff --git a/src/intel/compiler/brw_print.cpp b/src/intel/compiler/brw_print.cpp index ee2340bec09..ff4ae71ca5d 100644 --- a/src/intel/compiler/brw_print.cpp +++ b/src/intel/compiler/brw_print.cpp @@ -324,6 +324,7 @@ print_memory_logical_source(FILE *file, const fs_inst *inst, unsigned i) [MEMORY_MODE_UNTYPED] = "untyped", [MEMORY_MODE_SHARED_LOCAL] = "shared", [MEMORY_MODE_SCRATCH] = "scratch", + [MEMORY_MODE_CONSTANT] = "const", }; assert(inst->src[i].ud < ARRAY_SIZE(modes)); fprintf(file, " %s", modes[inst->src[i].ud]);