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i965/dri: Handle Y-tiled modifier

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This patch begins introducing how we'll actually handle the potentially
many modifiers coming in from the API, how we'll store them, and the
structure in the code to support it.

Prior to this patch, the Y-tiled modifier would be entirely ignored. It
shouldn't actually be used until this point because we've not bumped the
DRIimage extension version (which is a requirement to use modifiers).

Measuring later in the series with kmscube:
Linear:
Read bandwidth: 1048.44 MiB/s
Write bandwidth: 1483.17 MiB/s

Y-tiled:
Read bandwidth: 471.13 MiB/s
Write bandwidth: 589.10 MiB/s

Similar functionality was introduced and then reverted here:

commit 6a0d036483
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Thu Apr 21 20:14:58 2016 -0700

    i965: Always use Y-tiled buffers on SKL+

v2: Use last set bit instead of first set bit in modifiers to address
bug found by Daniel Stone.

v3: Use the new priority modifier selection thing. This nullifies the
bug fixed by v2 also.

v4: Get rid of modifier compaction which originally served another
purpose and now serves none (Jason)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Ben Widawsky 2016-11-04 12:34:40 -07:00
parent d78a36ea62
commit 7ce0405826
1 changed files with 14 additions and 4 deletions
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18
src/mesa/drivers/dri/i965/intel_screen.c
View file

@ -23,6 +23,7 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <drm_fourcc.h>
#include <errno.h>
#include <time.h>
#include <unistd.h>
@ -518,11 +519,13 @@ intel_destroy_image(__DRIimage *image)
enum modifier_priority {
MODIFIER_PRIORITY_INVALID = 0,
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_Y,
};
const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
};
static uint64_t
@ -530,11 +533,13 @@ select_best_modifier(struct gen_device_info *devinfo,
const uint64_t *modifiers,
const unsigned count)
{
enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
for (int i = 0; i < count; i++) {
switch (modifiers[i]) {
case I915_FORMAT_MOD_Y_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_Y);
break;
case DRM_FORMAT_MOD_LINEAR:
prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
break;
@ -575,6 +580,9 @@ intel_create_image_common(__DRIscreen *dri_screen,
case DRM_FORMAT_MOD_LINEAR:
tiling = I915_TILING_NONE;
break;
case I915_FORMAT_MOD_Y_TILED:
tiling = I915_TILING_Y;
break;
case DRM_FORMAT_MOD_INVALID:
if (modifiers)
return NULL;
@ -628,8 +636,8 @@ intel_create_image_with_modifiers(__DRIscreen *dri_screen,
const unsigned count,
void *loaderPrivate)
{
return intel_create_image_common(dri_screen, width, height, format, 0, NULL,
0, loaderPrivate);
return intel_create_image_common(dri_screen, width, height, format, 0,
modifiers, count, loaderPrivate);
}
static GLboolean
@ -1999,7 +2007,9 @@ intelAllocateBuffer(__DRIscreen *dri_screen,
if (intelBuffer == NULL)
return NULL;
/* The front and back buffers are color buffers, which are X tiled. */
/* The front and back buffers are color buffers, which are X tiled. GEN9+
* supports Y tiled and compressed buffers, but there is no way to plumb that
* through to here. */
uint32_t tiling = I915_TILING_X;
unsigned long pitch;
int cpp = format / 8;