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anv: add support for simple internal compute shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
This commit is contained in:
Lionel Landwerlin
parent
dbbcd5c32c
commit
7ca5c84804
1 changed files with 154 additions and 4 deletions
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@ -305,7 +305,14 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
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static void
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genX(emit_simpler_shader_init_compute)(struct anv_simple_shader *state)
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{
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unreachable("TODO");
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assert(state->cmd_buffer->state.current_pipeline == GPGPU);
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#if GFX_VERx10 >= 125
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struct anv_shader_bin *cs_bin = state->kernel;
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const struct brw_cs_prog_data *prog_data =
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(const struct brw_cs_prog_data *) cs_bin->prog_data;
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genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, prog_data->base.total_scratch);
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#endif
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}
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static void
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@ -328,7 +335,12 @@ genX(simple_shader_alloc_push)(struct anv_simple_shader *state, uint32_t size)
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size,
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ANV_UBO_ALIGNMENT);
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} else {
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unreachable("TODO");
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#if GFX_VERx10 >= 125
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return anv_state_stream_alloc(&state->cmd_buffer->general_state_stream,
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size, 64);
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#else
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return anv_cmd_buffer_alloc_dynamic_state(state->cmd_buffer, size, 64);
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#endif
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}
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}
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@ -341,7 +353,15 @@ genX(simple_shader_push_state_address)(struct anv_simple_shader *state,
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&state->cmd_buffer->device->dynamic_state_pool,
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push_state);
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} else {
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unreachable("TODO");
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#if GFX_VERx10 >= 125
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return anv_state_pool_state_address(
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&state->cmd_buffer->device->general_state_pool,
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push_state);
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#else
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return anv_state_pool_state_address(
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&state->cmd_buffer->device->dynamic_state_pool,
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push_state);
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#endif
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}
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}
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@ -438,7 +458,137 @@ genX(emit_simple_shader_dispatch)(struct anv_simple_shader *state,
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prim.InstanceCount = 1;
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}
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} else {
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unreachable("TODO");
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const struct intel_device_info *devinfo = device->info;
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const struct brw_cs_prog_data *prog_data =
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(const struct brw_cs_prog_data *) state->kernel->prog_data;
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const struct brw_cs_dispatch_info dispatch =
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brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
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#if GFX_VERx10 >= 125
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anv_batch_emit(batch, GENX(COMPUTE_WALKER), cw) {
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cw.SIMDSize = dispatch.simd_size / 16;
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cw.IndirectDataStartAddress = push_state.offset;
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cw.IndirectDataLength = push_state.alloc_size;
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cw.LocalXMaximum = prog_data->local_size[0] - 1;
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cw.LocalYMaximum = prog_data->local_size[1] - 1;
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cw.LocalZMaximum = prog_data->local_size[2] - 1;
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cw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
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dispatch.simd_size);
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cw.ThreadGroupIDYDimension = 1;
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cw.ThreadGroupIDZDimension = 1;
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cw.ExecutionMask = dispatch.right_mask;
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cw.PostSync.MOCS = anv_mocs(device, NULL, 0);
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cw.InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) {
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.KernelStartPointer = state->kernel->kernel.offset +
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brw_cs_prog_data_prog_offset(prog_data,
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dispatch.simd_size),
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.SamplerStatePointer = 0,
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.BindingTablePointer = 0,
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.BindingTableEntryCount = 0,
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.NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
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.SharedLocalMemorySize = encode_slm_size(GFX_VER,
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prog_data->base.total_shared),
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.NumberOfBarriers = prog_data->uses_barrier,
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};
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}
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#else
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const uint32_t vfe_curbe_allocation =
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ALIGN(prog_data->push.per_thread.regs * dispatch.threads +
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prog_data->push.cross_thread.regs, 2);
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/* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
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*
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* "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
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* the only bits that are changed are scoreboard related: Scoreboard
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* Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
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* these scoreboard related states, a MEDIA_STATE_FLUSH is
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* sufficient."
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*/
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genX(emit_apply_pipe_flushes)(batch, device, GPGPU, ANV_PIPE_CS_STALL_BIT,
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&state->cmd_buffer->state.pending_query_bits);
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anv_batch_emit(batch, GENX(MEDIA_VFE_STATE), vfe) {
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vfe.StackSize = 0;
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vfe.MaximumNumberofThreads =
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devinfo->max_cs_threads * devinfo->subslice_total - 1;
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vfe.NumberofURBEntries = 2;
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#if GFX_VER < 11
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vfe.ResetGatewayTimer = true;
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#endif
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vfe.URBEntryAllocationSize = 2;
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vfe.CURBEAllocationSize = vfe_curbe_allocation;
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if (prog_data->base.total_scratch) {
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/* Broadwell's Per Thread Scratch Space is in the range [0, 11]
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* where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
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*/
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vfe.PerThreadScratchSpace =
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ffs(prog_data->base.total_scratch) - 11;
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vfe.ScratchSpaceBasePointer =
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(struct anv_address) {
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.bo = anv_scratch_pool_alloc(device,
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&device->scratch_pool,
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MESA_SHADER_COMPUTE,
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prog_data->base.total_scratch),
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.offset = 0,
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};
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}
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}
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struct anv_state iface_desc_state =
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anv_cmd_buffer_alloc_dynamic_state(state->cmd_buffer,
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GENX(INTERFACE_DESCRIPTOR_DATA_length) * 4,
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64);
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struct GENX(INTERFACE_DESCRIPTOR_DATA) iface_desc = {
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.KernelStartPointer = state->kernel->kernel.offset +
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brw_cs_prog_data_prog_offset(prog_data,
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dispatch.simd_size),
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.SamplerCount = 0,
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.BindingTableEntryCount = 0,
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.BarrierEnable = prog_data->uses_barrier,
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.SharedLocalMemorySize = encode_slm_size(GFX_VER,
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prog_data->base.total_shared),
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.ConstantURBEntryReadOffset = 0,
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.ConstantURBEntryReadLength = prog_data->push.per_thread.regs,
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.CrossThreadConstantDataReadLength = prog_data->push.cross_thread.regs,
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#if GFX_VER >= 12
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/* TODO: Check if we are missing workarounds and enable mid-thread
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* preemption.
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*
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* We still have issues with mid-thread preemption (it was already
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* disabled by the kernel on gfx11, due to missing workarounds). It's
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* possible that we are just missing some workarounds, and could
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* enable it later, but for now let's disable it to fix a GPU in
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* compute in Car Chase (and possibly more).
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*/
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.ThreadPreemptionDisable = true,
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#endif
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.NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
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};
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GENX(INTERFACE_DESCRIPTOR_DATA_pack)(batch, iface_desc_state.map, &iface_desc);
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anv_batch_emit(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
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mid.InterfaceDescriptorTotalLength = iface_desc_state.alloc_size;
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mid.InterfaceDescriptorDataStartAddress = iface_desc_state.offset;
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}
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anv_batch_emit(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
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curbe.CURBEDataStartAddress = push_state.offset;
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curbe.CURBETotalDataLength = push_state.alloc_size;
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}
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anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
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ggw.SIMDSize = dispatch.simd_size / 16;
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ggw.ThreadDepthCounterMaximum = 0;
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ggw.ThreadHeightCounterMaximum = 0;
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ggw.ThreadWidthCounterMaximum = dispatch.threads - 1;
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ggw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
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dispatch.simd_size);
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ggw.ThreadGroupIDYDimension = 1;
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ggw.ThreadGroupIDZDimension = 1;
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ggw.RightExecutionMask = dispatch.right_mask;
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ggw.BottomExecutionMask = 0xffffffff;
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}
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#endif
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}
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}
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