diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index c365dbcc02d..6a8b7dad287 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1149,6 +1149,10 @@ radv_device_init_compiler_info(struct radv_device *device)
             .address32_hi = pdev->info.address32_hi,
             .rbplus_allowed = pdev->info.rbplus_allowed,
          },
+      .key =
+         {
+            .use_llvm = pdev->use_llvm,
+         },
       /* Debug/tracing */
       .debug =
          {
@@ -1163,7 +1167,6 @@ radv_device_init_compiler_info(struct radv_device *device)
             .dump_shaders = dump_shaders,
             .check_ir = !!(instance->debug_flags & RADV_DEBUG_CHECKIR),
             .printf_enabled = !!device->debug_nir.printf.buffer_addr,
-            .use_llvm = pdev->use_llvm,
             .trap_enabled = !!device->trap_handler_shader,
             .trap_excp_flags = instance->trap_excp_flags,
             .debug_report = &instance->vk.debug_report,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f4fafac647a..872c72d4da6 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -248,7 +248,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
                      struct radv_shader_stage *stage)
 {
    enum amd_gfx_level gfx_level = compiler_info->ac->gfx_level;
-   const bool use_llvm = compiler_info->debug.use_llvm;
+   const bool use_llvm = compiler_info->key.use_llvm;
    bool progress;
 
    /* Wave and workgroup size should already be filled. */
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index b611369fe50..01c8939bb10 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -2074,14 +2074,13 @@ radv_create_gs_copy_shader(const struct radv_compiler_info *compiler_info, struc
    gs_copy_stage.info.user_sgprs_locs = gs_copy_stage.args.user_sgprs_locs;
    gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask;
 
-   NIR_PASS(
-      _, nir, ac_nir_lower_intrinsics_to_args, &gs_copy_stage.args.ac,
-      &(ac_nir_lower_intrinsics_to_args_options){.gfx_level = compiler_info->ac->gfx_level,
-                                                 .has_ls_vgpr_init_bug = compiler_info->ac->has_ls_vgpr_init_bug,
-                                                 .hw_stage = AC_HW_VERTEX_SHADER,
-                                                 .wave_size = 64,
-                                                 .workgroup_size = 64,
-                                                 .use_llvm = compiler_info->debug.use_llvm});
+   NIR_PASS(_, nir, ac_nir_lower_intrinsics_to_args, &gs_copy_stage.args.ac,
+            &(ac_nir_lower_intrinsics_to_args_options){.gfx_level = compiler_info->ac->gfx_level,
+                                                       .has_ls_vgpr_init_bug = compiler_info->ac->has_ls_vgpr_init_bug,
+                                                       .hw_stage = AC_HW_VERTEX_SHADER,
+                                                       .wave_size = 64,
+                                                       .workgroup_size = 64,
+                                                       .use_llvm = compiler_info->key.use_llvm});
    NIR_PASS(_, nir, radv_nir_lower_abi, compiler_info->ac->gfx_level, &gs_copy_stage, gfx_state, compiler_info->hw.address32_hi);
 
    NIR_PASS(_, nir, ac_nir_lower_global_access);
diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c
index d85ea40217e..21248e3258d 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -421,7 +421,7 @@ radv_rt_nir_to_asm(const struct radv_compiler_info *compiler_info, struct radv_r
          .stack_alignment = 16,
          .localized_loads = true,
          .vectorizer_callback = ac_nir_mem_vectorize_callback,
-         .vectorizer_data = &(struct ac_nir_config){compiler_info->ac->gfx_level, !compiler_info->debug.use_llvm},
+         .vectorizer_data = &(struct ac_nir_config){compiler_info->ac->gfx_level, !compiler_info->key.use_llvm},
       };
       nir_lower_shader_calls(stage->nir, &opts, &resume_shaders, &num_resume_shaders, mem_ctx);
    }
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 818451fc60a..ece5fedf07f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -59,7 +59,7 @@ get_nir_options_for_stage(struct radv_compiler_info *compiler_info, mesa_shader_
    const bool split_fma =
       (stage <= MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH) && compiler_info->cache_key->split_fma;
 
-   ac_nir_set_options(compiler_info->ac, compiler_info->debug.use_llvm, options);
+   ac_nir_set_options(compiler_info->ac, compiler_info->key.use_llvm, options);
 
    options->lower_ffma16 = split_fma || compiler_info->ac->gfx_level < GFX9;
    options->lower_ffma32 = split_fma || compiler_info->ac->gfx_level < GFX10_3;
@@ -726,7 +726,7 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct
    NIR_PASS(_, nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 
    bool gfx7minus = compiler_info->ac->gfx_level <= GFX7;
-   bool use_llvm = compiler_info->debug.use_llvm;
+   bool use_llvm = compiler_info->key.use_llvm;
 
    NIR_PASS(_, nir, nir_lower_subgroups,
             &(struct nir_lower_subgroups_options){
@@ -3318,10 +3318,10 @@ shader_compile(const struct radv_compiler_info *compiler_info, struct nir_shader
    struct radv_shader_binary *binary = NULL;
 
 #if AMD_LLVM_AVAILABLE
-   if (compiler_info->debug.use_llvm || options->dump_shader || options->record_ir)
+   if (compiler_info->key.use_llvm || options->dump_shader || options->record_ir)
       ac_init_llvm_once();
 
-   if (compiler_info->debug.use_llvm) {
+   if (compiler_info->key.use_llvm) {
       llvm_compile_shader(options, info, shader_count, shaders, &binary, args);
 #else
    if (false) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 532471616f4..2c0b2c32e18 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -520,6 +520,10 @@ struct radv_compiler_info {
       bool rbplus_allowed;
    } hw;
 
+   struct {
+      bool use_llvm;
+   } key;
+
    /* Debug/tracing */
    struct {
       bool dump_spirv;
@@ -533,7 +537,6 @@ struct radv_compiler_info {
       VkShaderStageFlags dump_shaders;
       bool check_ir;
       bool printf_enabled;
-      bool use_llvm;
       bool trap_enabled;
       uint64_t trap_excp_flags;
       struct vk_debug_report *debug_report;
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 2c2b394b3a6..23fddc9024d 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -379,8 +379,8 @@ radv_init_shader_args(const struct radv_compiler_info *compiler_info, struct rad
 {
    memset(state->args, 0, sizeof(*state->args));
 
-   state->args->explicit_scratch_args = !compiler_info->debug.use_llvm;
-   state->args->remap_spi_ps_input = !compiler_info->debug.use_llvm;
+   state->args->explicit_scratch_args = !compiler_info->key.use_llvm;
+   state->args->remap_spi_ps_input = !compiler_info->key.use_llvm;
 
    for (int i = 0; i < MAX_SETS; i++)
       state->args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 913d4f5971f..f07b63c3fec 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -1408,7 +1408,7 @@ radv_link_shaders_info(const struct radv_compiler_info *compiler_info, struct ra
             compiler_info->ac->gfx_level, MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches,
             gfx_state->ts.patch_control_points, tcs_stage->info.tcs.tcs_vertices_out);
 
-         if (!compiler_info->debug.use_llvm) {
+         if (!compiler_info->key.use_llvm) {
             /* When the number of TCS input and output vertices are the same (typically 3):
              * - There is an equal amount of LS and HS invocations
              * - In case of merged LSHS shaders, the LS and HS halves of the shader always process