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freedreno/registers: fix RBBM_PRIMCTR understanding and usage
RBBM_PRIMCTR registers are used for different pipeline statistics that can be queried, but current usage was wrong in some cases. Comments in the register file are updated, and the per-statistic register index mapping is updated accordingly. Fixes on a750: test_query_pipeline_statistics in vkd3d-proton arb_query_buffer_object failures in piglit (zink) Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32900>
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parent
3fed68b607
commit
7c927144b3
5 changed files with 22 additions and 46 deletions
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@ -4,7 +4,6 @@ test_early_depth_stencil_tests,Fail
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test_index_buffer_edge_case_stream_output,Fail
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test_multisample_resolve_strongly_typed,Fail
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test_primitive_restart_list_topology_stream_output,Fail
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test_query_pipeline_statistics,Fail
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test_sampler_rounding,Fail
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test_shader_instructions,Fail
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test_shader_sm66_quad_op_semantics,Fail
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@ -2633,27 +2633,27 @@ to upconvert to 32b float internally?
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vertices in, number of primnitives assembled etc.
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-->
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<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
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<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- IA_VERTICES -->
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<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
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<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
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<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- IA_PRIMITIVES -->
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<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
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<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
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<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- VS_INVOCATIONS -->
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<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
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<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
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<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- HS_INVOCATIONS -->
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<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
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<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
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<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- DS_INVOCATIONS -->
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<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
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<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
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<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- GS_INVOCATIONS -->
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<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
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<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
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<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- GS_PRIMITIVES -->
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<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
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<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
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<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- C_INVOCATIONS -->
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<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
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<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
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<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- C_PRIMITIVES -->
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<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
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<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
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<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- PS_INVOCATIONS -->
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<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
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<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
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<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> <!-- CS_INVOCATIONS -->
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<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
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<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
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@ -388,14 +388,11 @@ statistics_index(uint32_t *statistics)
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switch (1 << stat) {
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case VK_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_VERTICES_BIT:
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case VK_QUERY_PIPELINE_STATISTIC_VERTEX_SHADER_INVOCATIONS_BIT:
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return 0;
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case VK_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_PRIMITIVES_BIT:
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return 1;
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case VK_QUERY_PIPELINE_STATISTIC_TESSELLATION_CONTROL_SHADER_PATCHES_BIT:
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case VK_QUERY_PIPELINE_STATISTIC_VERTEX_SHADER_INVOCATIONS_BIT:
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return 2;
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case VK_QUERY_PIPELINE_STATISTIC_TESSELLATION_EVALUATION_SHADER_INVOCATIONS_BIT:
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return 4;
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case VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_INVOCATIONS_BIT:
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return 5;
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case VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT:
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@ -406,6 +403,10 @@ statistics_index(uint32_t *statistics)
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return 8;
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case VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT:
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return 9;
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case VK_QUERY_PIPELINE_STATISTIC_TESSELLATION_CONTROL_SHADER_PATCHES_BIT:
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return 3;
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case VK_QUERY_PIPELINE_STATISTIC_TESSELLATION_EVALUATION_SHADER_INVOCATIONS_BIT:
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return 4;
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case VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT:
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return 10;
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default:
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@ -403,18 +403,15 @@ FD_DEFINE_CAST(fd_acc_query_sample, fd6_pipeline_stats_sample);
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* ----------------------------+--------------------------------------------+----------------
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* IA_VERTICES | INPUT_ASSEMBLY_VERTICES | RBBM_PRIMCTR_0
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* IA_PRIMITIVES | INPUT_ASSEMBLY_PRIMITIVES | RBBM_PRIMCTR_1
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* VS_INVOCATIONS | VERTEX_SHADER_INVOCATIONS | RBBM_PRIMCTR_0
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* VS_INVOCATIONS | VERTEX_SHADER_INVOCATIONS | RBBM_PRIMCTR_2
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* GS_INVOCATIONS | GEOMETRY_SHADER_INVOCATIONS | RBBM_PRIMCTR_5
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* GS_PRIMITIVES | GEOMETRY_SHADER_PRIMITIVES | RBBM_PRIMCTR_6
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* C_INVOCATIONS | CLIPPING_INVOCATIONS | RBBM_PRIMCTR_7
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* C_PRIMITIVES | CLIPPING_PRIMITIVES | RBBM_PRIMCTR_8
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* PS_INVOCATIONS | FRAGMENT_SHADER_INVOCATIONS | RBBM_PRIMCTR_9
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* HS_INVOCATIONS | TESSELLATION_CONTROL_SHADER_PATCHES | RBBM_PRIMCTR_2
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* HS_INVOCATIONS | TESSELLATION_CONTROL_SHADER_PATCHES | RBBM_PRIMCTR_3
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* DS_INVOCATIONS | TESSELLATION_EVALUATION_SHADER_INVOCATIONS | RBBM_PRIMCTR_4
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* CS_INVOCATIONS | COMPUTE_SHADER_INVOCATIONS | RBBM_PRIMCTR_10
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*
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* Note that "Vertices corresponding to incomplete primitives may contribute to the count.",
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* in our case they do not, so IA_VERTICES and VS_INVOCATIONS are the same thing.
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*/
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enum stats_type {
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@ -454,13 +451,13 @@ stats_counter_index(struct fd_acc_query *aq)
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switch (aq->base.index) {
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case PIPE_STAT_QUERY_IA_VERTICES: return 0;
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case PIPE_STAT_QUERY_IA_PRIMITIVES: return 1;
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case PIPE_STAT_QUERY_VS_INVOCATIONS: return 0;
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case PIPE_STAT_QUERY_VS_INVOCATIONS: return 2;
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case PIPE_STAT_QUERY_GS_INVOCATIONS: return 5;
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case PIPE_STAT_QUERY_GS_PRIMITIVES: return 6;
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case PIPE_STAT_QUERY_C_INVOCATIONS: return 7;
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case PIPE_STAT_QUERY_C_PRIMITIVES: return 8;
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case PIPE_STAT_QUERY_PS_INVOCATIONS: return 9;
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case PIPE_STAT_QUERY_HS_INVOCATIONS: return 2;
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case PIPE_STAT_QUERY_HS_INVOCATIONS: return 3;
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case PIPE_STAT_QUERY_DS_INVOCATIONS: return 4;
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case PIPE_STAT_QUERY_CS_INVOCATIONS: return 10;
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default:
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@ -473,10 +470,10 @@ log_pipeline_stats(struct fd6_pipeline_stats_sample *ps, unsigned idx)
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{
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#ifdef DEBUG_COUNTERS
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const char *labels[] = {
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"VS_INVOCATIONS",
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"IA_VERTICES",
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"IA_PRIMITIVES",
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"VS_INVOCATIONS",
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"HS_INVOCATIONS",
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"??",
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"DS_INVOCATIONS",
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"GS_INVOCATIONS",
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"GS_PRIMITIVES",
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@ -100,27 +100,6 @@ spec@arb_internalformat_query2@all internalformat_<x>_type pname checks@GL_INTER
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spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex,Fail
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spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2' on GL_PROGRAM_INPUT,Fail
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spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2[1][0]' on GL_PROGRAM_INPUT,Fail
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spec@arb_query_buffer_object@coherency,Fail
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spec@arb_query_buffer_object@coherency@index-buffer-GL_TESS_CONTROL_SHADER_PATCHES,Fail
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spec@arb_query_buffer_object@coherency@indirect-dispatch-GL_TESS_CONTROL_SHADER_PATCHES,Fail
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spec@arb_query_buffer_object@coherency@indirect-draw-GL_TESS_CONTROL_SHADER_PATCHES,Fail
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spec@arb_query_buffer_object@coherency@indirect-draw-count-GL_TESS_CONTROL_SHADER_PATCHES,Fail
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spec@arb_query_buffer_object@qbo,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC-GL_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC-GL_UNSIGNED_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC-GL_UNSIGNED_INT64_ARB,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_AFTER-GL_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_BEFORE-GL_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_BEFORE-GL_UNSIGNED_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-ASYNC_CPU_READ_BEFORE-GL_UNSIGNED_INT64_ARB,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC-GL_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC-GL_UNSIGNED_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC-GL_UNSIGNED_INT64_ARB,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT,Fail
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spec@arb_query_buffer_object@qbo@query-GL_TESS_CONTROL_SHADER_PATCHES-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT64_ARB,Fail
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spec@arb_sample_locations@test,Fail
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spec@arb_sample_locations@test@MSAA: 1- X: 0- Y: 0- Grid: false,Fail
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spec@arb_sample_locations@test@MSAA: 1- X: 0- Y: 0- Grid: true,Fail
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