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nv50: add some texture formats

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This commit is contained in:
Ben Skeggs 2008-07-11 21:19:41 +10:00
parent 62100692b8
commit 7c745de749
4 changed files with 90 additions and 13 deletions
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2
src/gallium/drivers/nv50/nv50_program.c
View file

@ -1701,6 +1701,8 @@ nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
if (p->buffer)
pipe_buffer_reference(ws, &p->buffer, NULL);
nv50->screen->nvws->res_free(&p->data);
p->translated = 0;
}

6
src/gallium/drivers/nv50/nv50_screen.c
View file

@ -51,7 +51,13 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
case PIPE_TEXTURE:
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_A1R5G5B5_UNORM:
case PIPE_FORMAT_A4R4G4B4_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
case PIPE_FORMAT_L8_UNORM:
case PIPE_FORMAT_A8_UNORM:
case PIPE_FORMAT_I8_UNORM:
case PIPE_FORMAT_A8L8_UNORM:
return TRUE;
default:
break;

93
src/gallium/drivers/nv50/nv50_tex.c
View file

@ -25,6 +25,81 @@
#include "nouveau/nouveau_stateobj.h"
static int
nv50_tex_construct(struct nouveau_stateobj *so, struct nv50_miptree *mt)
{
switch (mt->base.format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_8_8_8_8);
break;
case PIPE_FORMAT_A1R5G5B5_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_1_5_5_5);
break;
case PIPE_FORMAT_A4R4G4B4_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_4_4_4_4);
break;
case PIPE_FORMAT_R5G6B5_UNORM:
so_data(so, NV50TIC_0_0_MAPA_ONE | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_5_6_5);
break;
case PIPE_FORMAT_L8_UNORM:
so_data(so, NV50TIC_0_0_MAPA_ONE | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_8);
break;
case PIPE_FORMAT_A8_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_8);
break;
case PIPE_FORMAT_I8_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_8);
break;
case PIPE_FORMAT_A8L8_UNORM:
so_data(so, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_FMT_8_8);
break;
default:
return 1;
}
so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW, 0, 0);
so_data (so, 0xd0005000);
so_data (so, 0x00300000);
so_data (so, mt->base.width[0]);
so_data (so, (mt->base.depth[0] << 16) | mt->base.height[0]);
so_data (so, 0x03000000);
so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH, 0, 0);
return 0;
}
void
nv50_tex_validate(struct nv50_context *nv50)
{
@ -37,19 +112,11 @@ nv50_tex_validate(struct nv50_context *nv50)
so_data (so, NV50_CB_TIC);
so_method(so, tesla, 0x40000f04, nv50->miptree_nr * 8);
for (i = 0; i < nv50->miptree_nr; i++) {
struct nv50_miptree *mt = nv50->miptree[i];
so_data (so, 0x2a712488);
so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM |
NOUVEAU_BO_LOW, 0, 0);
so_data (so, 0xd0005000);
so_data (so, 0x00300000);
so_data (so, mt->base.width[0]);
so_data (so, (mt->base.depth[0] << 16) |
mt->base.height[0]);
so_data (so, 0x03000000);
so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM |
NOUVEAU_BO_HIGH, 0, 0);
if (nv50_tex_construct(so, nv50->miptree[i])) {
NOUVEAU_ERR("failed tex validate\n");
so_ref(NULL, &so);
return;
}
}
so_ref(so, &nv50->state.tic_upload);

2
src/gallium/drivers/nv50/nv50_texture.h
View file

@ -45,6 +45,8 @@
#define NV50TIC_0_0_TYPEB_UNORM 0x00000080
#define NV50TIC_0_0_FMT_MASK 0x0000003c
#define NV50TIC_0_0_FMT_8_8_8_8 0x00000008
#define NV50TIC_0_0_FMT_4_4_4_4 0x00000012
#define NV50TIC_0_0_FMT_1_5_5_5 0x00000013
#define NV50TIC_0_0_FMT_5_6_5 0x00000015
#define NV50TIC_0_0_FMT_8_8 0x00000018
#define NV50TIC_0_0_FMT_8 0x0000001d