mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-06 13:48:06 +02:00
radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE
To make them readable by shaders, only needed on GFX10+.
This also fixes corruption with Control and MSAA.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10610>
(cherry picked from commit 33ede796d5)
This commit is contained in:
parent
7ccaf80920
commit
7c3ec53a12
7 changed files with 34 additions and 34 deletions
|
|
@ -1921,7 +1921,7 @@
|
|||
"description": "radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE",
|
||||
"nominated": true,
|
||||
"nomination_type": 0,
|
||||
"resolution": 0,
|
||||
"resolution": 1,
|
||||
"master_sha": null,
|
||||
"because_sha": null
|
||||
},
|
||||
|
|
|
|||
|
|
@ -121,36 +121,3 @@ dEQP-VK.drm_format_modifiers.create_list_modifiers.r16g16b16_uscaled,Crash
|
|||
dEQP-VK.image.mismatched_formats.sparse_image_read.d16_unorm_with_r16,Crash
|
||||
dEQP-VK.image.mismatched_formats.sparse_image_read.d32_sfloat_with_r32f,Crash
|
||||
dEQP-VK.image.mismatched_formats.sparse_image_read.s8_uint_with_r8ui,Crash
|
||||
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.keep.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.keep.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.replace.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.replace.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.keep.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.keep.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.replace.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.replace.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.keep.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.keep.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.replace.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.noshaderrate.replace.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.keep.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.replace.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.keep.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.noattachment.shaderrate.replace.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.keep.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.keep.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.replace.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.replace.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.keep.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.keep.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.replace.keep.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.replace.keep.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.keep.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.replace.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.replace.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.keep.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.replace.replace.151x431.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.keep.replace.256x256.samples8.vs,Fail
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.noshaderrate.keep.replace.151x431.samples8.vsœ
|
||||
dEQP-VK.fragment_shading_rate.fragstencil.dynamic.attachment.shaderrate.replace.replace.256x256.samples8.vs
|
||||
|
|
|
|||
|
|
@ -887,6 +887,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
|
|||
info->has_image_load_dcc_bug = info->family == CHIP_DIMGREY_CAVEFISH ||
|
||||
info->family == CHIP_VANGOGH;
|
||||
|
||||
/* DB has a bug when ITERATE_256 is set to 1 that can cause a hang. The
|
||||
* workaround is to set DECOMPRESS_ON_Z_PLANES to 2 for 4X MSAA D/S images.
|
||||
*/
|
||||
info->has_two_planes_iterate256_bug = info->chip_class == GFX10;
|
||||
|
||||
/* Support for GFX10.3 was added with F32_ME_FEATURE_VERSION_31 but the
|
||||
* firmware version wasn't bumped.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ struct radeon_info {
|
|||
bool has_ls_vgpr_init_bug;
|
||||
bool has_zero_index_buffer_bug;
|
||||
bool has_image_load_dcc_bug;
|
||||
bool has_two_planes_iterate256_bug;
|
||||
bool has_32bit_predication;
|
||||
bool has_3d_cube_border_color_mipmap;
|
||||
|
||||
|
|
|
|||
|
|
@ -6579,6 +6579,14 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v
|
|||
if (iview->vk_format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1)
|
||||
max_zplanes = 2;
|
||||
|
||||
/* Workaround for a DB hang when ITERATE_256 is set to 1. Only affects 4X MSAA D/S images. */
|
||||
if (device->physical_device->rad_info.has_two_planes_iterate256_bug &&
|
||||
radv_image_get_iterate256(device, iview->image) &&
|
||||
!radv_image_tile_stencil_disabled(device, iview->image) &&
|
||||
iview->image->info.samples == 4) {
|
||||
max_zplanes = 1;
|
||||
}
|
||||
|
||||
max_zplanes = max_zplanes + 1;
|
||||
} else {
|
||||
if (iview->vk_format == VK_FORMAT_D16_UNORM) {
|
||||
|
|
@ -6682,8 +6690,12 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
|
|||
ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
|
||||
|
||||
if (device->physical_device->rad_info.chip_class >= GFX10) {
|
||||
bool iterate256 = radv_image_get_iterate256(device, iview->image);
|
||||
|
||||
ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
|
||||
ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
|
||||
ds->db_z_info |= S_028040_ITERATE_256(iterate256);
|
||||
ds->db_stencil_info |= S_028044_ITERATE_256(iterate256);
|
||||
} else {
|
||||
ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
|
||||
ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
|
||||
|
|
|
|||
|
|
@ -926,6 +926,10 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
|
|||
S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
|
||||
}
|
||||
|
||||
if (radv_image_get_iterate256(device, image)) {
|
||||
state[6] |= S_00A018_ITERATE_256(1);
|
||||
}
|
||||
|
||||
/* Initialize the sampler view for FMASK. */
|
||||
if (fmask_state) {
|
||||
if (radv_image_has_fmask(image)) {
|
||||
|
|
|
|||
|
|
@ -2076,6 +2076,17 @@ radv_get_htile_initial_value(const struct radv_device *device, const struct radv
|
|||
return initial_value;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
radv_image_get_iterate256(struct radv_device *device, struct radv_image *image)
|
||||
{
|
||||
/* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
|
||||
return device->physical_device->rad_info.chip_class >= GFX10 &&
|
||||
(image->usage & (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT |
|
||||
VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
|
||||
radv_image_is_tc_compat_htile(image) &&
|
||||
image->info.samples > 1;
|
||||
}
|
||||
|
||||
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family,
|
||||
uint32_t queue_family);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue