diff --git a/.pick_status.json b/.pick_status.json
index a4ebe86f0de..4a4af598da9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -337,7 +337,7 @@
         "description": "isl: only bump the min row pitch for display when not specified",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "a3a4517f4147a0a7c1b34a4bcd42de45d552df5f"
     },
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 0ab9937a2c8..0cc2c3ef007 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1479,10 +1479,20 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
     *    "When using linear memory, this must be at least 64 byte aligned."
     *
     * However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
-    * we need a larger pitch of 256 bytes.  We do that just in case.
+    * we need a larger pitch of 256 bytes.
+    *
+    * If the ISL caller didn't specify a row_pitch_B, then we should assume
+    * the NVIDIA/AMD requirements. Otherwise, if we have a specified
+    * row_pitch_B, this is probably because the caller is trying to import a
+    * buffer. In that case we limit the minimum row pitch to the Intel HW
+    * requirement.
     */
-   if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
-      alignment = isl_align(alignment, 256);
+   if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
+      if (surf_info->row_pitch_B == 0)
+         alignment = isl_align(alignment, 256);
+      else
+         alignment = isl_align(alignment, 64);
+   }
 
    return alignment;
 }