diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h
index cd0f41dffdf..762a85f0bdb 100644
--- a/src/amd/common/ac_nir.h
+++ b/src/amd/common/ac_nir.h
@@ -361,6 +361,35 @@ ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4);
 bool
 ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level);
 
+#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \
+   do { \
+      if ((store_val)->bit_size >= 32) { \
+         const unsigned store_write_mask = (write_mask); \
+         const unsigned store_const_offset = (const_offset); \
+         func((b), (store_val), __VA_ARGS__); \
+      } else { \
+         u_foreach_bit(c, (write_mask)) { \
+            const unsigned store_write_mask = 1; \
+            const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \
+            nir_def *store_component = nir_channel(b, (store_val), c); \
+            func((b), store_component, __VA_ARGS__); \
+         } \
+      } \
+   } while (0)
+
+#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \
+   do { \
+      const unsigned load_bit_size = MAX2(32, (bit_size)); \
+      (load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \
+      if ((bit_size) < load_bit_size) { \
+         if ((hi_16bit)) { \
+            (load) = nir_unpack_32_2x16_split_y(b, load); \
+         } else { \
+            (load) = nir_unpack_32_2x16_split_x(b, load); \
+         } \
+      } \
+   } while (0)
+
 #ifdef __cplusplus
 }
 #endif