fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 04:50:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/brw: Allow immediates in the BFE instruction on Gfx12+

Browse source 
We weren't allowing immediates in BFE at all.  Gfx12+ supports
immediates in src0 (value) and src2 (width), but not src1 (offset).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31437>
This commit is contained in:
Kenneth Graunke 2024-09-21 01:50:49 -07:00 • committed by Marge Bot
parent d19e2597ce
commit 7bed11fbde
1 changed files with 9 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/intel/compiler/brw_fs_combine_constants.cpp
View file

@ -996,7 +996,7 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst
switch (inst->opcode) {
case BRW_OPCODE_ADD3:
/* ADD3 only exists on Gfx12.5+. */
case BRW_OPCODE_BFE:
return true;
case BRW_OPCODE_CSEL:
@ -1026,8 +1026,13 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
* only propagates into src0. It's possible that src2 works for W or UW MAD
* on Gfx12.5.
*/
if (src_idx != 0)
return false;
if (inst->opcode == BRW_OPCODE_BFE) {
if (src_idx == 1)
return false;
} else {
if (src_idx != 0)
return false;
}
if (!supports_src_as_imm(devinfo, inst))
return false;
@ -1302,6 +1307,7 @@ brw_fs_opt_combine_constants(fs_visitor &s)
* 16-bits, it would be better to add both sources with
* allow_one_constant=true as is done for SEL.
*/
case BRW_OPCODE_BFE:
case BRW_OPCODE_ADD3:
case BRW_OPCODE_CSEL:
case BRW_OPCODE_MAD: {
@ -1319,7 +1325,6 @@ brw_fs_opt_combine_constants(fs_visitor &s)
break;
}
case BRW_OPCODE_BFE:
case BRW_OPCODE_BFI2:
case BRW_OPCODE_LRP:
for (int i = 0; i < inst->sources; i++) {