From 7be8af1dada5bc00211042b963e8dd993f8cdb74 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 18 Mar 2026 15:21:10 +0200 Subject: [PATCH] anv: deal with Wa 14024015672 on the blorp path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is going to bite us a lot more when RCC BTP+BTI is enabled. In particular this test will hang pretty reliably on LNL : dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.suballocation.multisample_resolve.layers_3.r32g32_sfloat.samples_4_baseLayer1 Signed-off-by: Lionel Landwerlin Fixes: f66ff97d58 ("drirc/anv: implement steps to disable RHWO for Wa_14024015672") Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/anv_genX.h | 13 +++++++++++++ src/intel/vulkan/genX_blorp_exec.c | 9 +++++++++ src/intel/vulkan/genX_cmd_draw.c | 8 ++------ 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 42368b2b066..6829fe7a821 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -554,3 +554,16 @@ genX(cmd_buffer_post_dispatch_wa)(struct anv_cmd_buffer *cmd_buffer) "Wa_14025112257"); } } + +static inline void +genX(cmd_buffer_rhwo_wa_14024015672)(struct anv_cmd_buffer *cmd_buffer, + bool msaa_enabled) +{ + struct anv_device *device = cmd_buffer->device; + const bool rhwo_opt_enable = + !device->physical->instance->intel_enable_wa_14024015672_msaa && + msaa_enabled; + if (intel_needs_workaround(device->info, 14024015672) && + cmd_buffer->state.pending_rhwo_optimization_enabled != rhwo_opt_enable) + cmd_buffer->state.pending_rhwo_optimization_enabled = rhwo_opt_enable; +} diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 410246dcd56..c55cac45059 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -304,6 +304,15 @@ blorp_exec_on_render(struct blorp_batch *batch, genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0, params->y1 - params->y0, scale); + /* With Wa_14024015672, RHWO is initially disabled. We enable it for MSAA + * draws and disable for single sample unless explicitly disabled via drirc + * key. + */ +#if INTEL_WA_14024015672_GFX_VER + genX(cmd_buffer_rhwo_wa_14024015672)(cmd_buffer, params->num_samples > 1); +#endif + + #if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c index 18e33768f19..cd8c3c08e6d 100644 --- a/src/intel/vulkan/genX_cmd_draw.c +++ b/src/intel/vulkan/genX_cmd_draw.c @@ -830,12 +830,8 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer) * drirc key. */ #if INTEL_WA_14024015672_GFX_VER - if (intel_needs_workaround(device->info, 14024015672) && - BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES)) { - cmd_buffer->state.pending_rhwo_optimization_enabled = - !device->physical->instance->intel_enable_wa_14024015672_msaa && - dyn->ms.rasterization_samples > 1; - } + genX(cmd_buffer_rhwo_wa_14024015672)(cmd_buffer, + dyn->ms.rasterization_samples > 1); #endif /* Apply any pending pipeline flushes we may have. We want to apply them