radv: extend the dirty bits to 64-bit

For future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9603>
This commit is contained in:
Samuel Pitoiset 2021-03-15 17:51:27 +01:00 committed by Marge Bot
parent 0acd7df67b
commit 7bdd569d7e
3 changed files with 64 additions and 64 deletions

View file

@ -112,8 +112,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
const struct radv_dynamic_state *src)
{
struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
uint32_t copy_mask = src->mask;
uint32_t dest_mask = 0;
uint64_t copy_mask = src->mask;
uint64_t dest_mask = 0;
dest->discard_rectangle.count = src->discard_rectangle.count;
dest->sample_location.count = src->sample_location.count;
@ -5482,7 +5482,7 @@ static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
return true;
uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
uint64_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
/* Index, vertex and streamout buffers don't change context regs, and
* pipeline is already handled.

View file

@ -1339,7 +1339,7 @@ si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
}
}
static unsigned radv_dynamic_state_mask(VkDynamicState state)
static uint64_t radv_dynamic_state_mask(VkDynamicState state)
{
switch(state) {
case VK_DYNAMIC_STATE_VIEWPORT:
@ -1395,9 +1395,9 @@ static unsigned radv_dynamic_state_mask(VkDynamicState state)
}
}
static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
static uint64_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
uint32_t states = RADV_DYNAMIC_ALL;
uint64_t states = RADV_DYNAMIC_ALL;
/* If rasterization is disabled we do not care about any of the
* dynamic states, since they are all rasterization related only,
@ -1559,8 +1559,8 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
{
uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
uint32_t states = needed_states;
uint64_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
uint64_t states = needed_states;
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];

View file

@ -955,64 +955,64 @@ struct radv_buffer {
};
enum radv_dynamic_state_bits {
RADV_DYNAMIC_VIEWPORT = 1 << 0,
RADV_DYNAMIC_SCISSOR = 1 << 1,
RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
RADV_DYNAMIC_CULL_MODE = 1 << 12,
RADV_DYNAMIC_FRONT_FACE = 1 << 13,
RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
RADV_DYNAMIC_STENCIL_OP = 1 << 20,
RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
RADV_DYNAMIC_FRAGMENT_SHADING_RATE = 1 << 22,
RADV_DYNAMIC_ALL = (1 << 23) - 1,
RADV_DYNAMIC_VIEWPORT = 1ull << 0,
RADV_DYNAMIC_SCISSOR = 1ull << 1,
RADV_DYNAMIC_LINE_WIDTH = 1ull << 2,
RADV_DYNAMIC_DEPTH_BIAS = 1ull << 3,
RADV_DYNAMIC_BLEND_CONSTANTS = 1ull << 4,
RADV_DYNAMIC_DEPTH_BOUNDS = 1ull << 5,
RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1ull << 6,
RADV_DYNAMIC_STENCIL_WRITE_MASK = 1ull << 7,
RADV_DYNAMIC_STENCIL_REFERENCE = 1ull << 8,
RADV_DYNAMIC_DISCARD_RECTANGLE = 1ull << 9,
RADV_DYNAMIC_SAMPLE_LOCATIONS = 1ull << 10,
RADV_DYNAMIC_LINE_STIPPLE = 1ull << 11,
RADV_DYNAMIC_CULL_MODE = 1ull << 12,
RADV_DYNAMIC_FRONT_FACE = 1ull << 13,
RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1ull << 14,
RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1ull << 15,
RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1ull << 16,
RADV_DYNAMIC_DEPTH_COMPARE_OP = 1ull << 17,
RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1ull << 18,
RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1ull << 19,
RADV_DYNAMIC_STENCIL_OP = 1ull << 20,
RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
RADV_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
RADV_DYNAMIC_ALL = (1ull << 23) - 1,
};
enum radv_cmd_dirty_bits {
/* Keep the dynamic state dirty bits in sync with
* enum radv_dynamic_state_bits */
RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE = 1 << 22,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 23) - 1,
RADV_CMD_DIRTY_PIPELINE = 1 << 23,
RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 24,
RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 25,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 26,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 27,
RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1ull << 0,
RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1ull << 1,
RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1ull << 2,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1ull << 3,
RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1ull << 4,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1ull << 5,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1ull << 6,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1ull << 7,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1ull << 8,
RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1ull << 9,
RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1ull << 10,
RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1ull << 11,
RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1ull << 12,
RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1ull << 13,
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1ull << 14,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1ull << 15,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1ull << 16,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1ull << 17,
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1ull << 18,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1ull << 19,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1ull << 20,
RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 23) - 1,
RADV_CMD_DIRTY_PIPELINE = 1ull << 23,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 24,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 25,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 26,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 27,
};
enum radv_cmd_flush_bits {
@ -1107,10 +1107,10 @@ struct radv_sample_locations_state {
struct radv_dynamic_state {
/**
* Bitmask of (1 << VK_DYNAMIC_STATE_*).
* Bitmask of (1ull << VK_DYNAMIC_STATE_*).
* Defines the set of saved dynamic state.
*/
uint32_t mask;
uint64_t mask;
struct radv_viewport_state viewport;
@ -1306,7 +1306,7 @@ struct radv_cmd_state {
unsigned vb_size;
bool predicating;
uint32_t dirty;
uint64_t dirty;
uint32_t prefetch_L2_mask;