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brw: Properly set 'desc as register' for SEND in assembler

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The non-split SEND case was missing setting this.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38876>
This commit is contained in:
Caio Oliveira 2025-11-26 23:21:26 -08:00 • committed by Marge Bot
parent 308da55f1a
commit 7bd238fa5a
3 changed files with 8 additions and 2 deletions
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6
src/intel/compiler/brw/brw_gram.y
View file

@ -947,6 +947,12 @@ sendinstruction:
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $5);
if ($6.file != ARF &&
$6.nr != BRW_ARF_ADDRESS &&
$6.subnr != 0) {
error(&@2, "SEND with indirect desc must use a0.0\n");
}
brw_eu_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_bits(brw_last_inst, 127, 96, $7);
brw_eu_inst_set_sfid(p->devinfo, brw_last_inst, $8);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);

2
src/intel/compiler/brw/tests/gen9/send.expected
View file

@ -246,7 +246,7 @@
31 00 60 06 e0 3a 00 20 e0 0e 8d 06 37 00 08 92
31 00 60 06 e0 3a 00 20 00 01 8d 06 07 00 0a 14
31 00 60 06 e0 3a 00 20 c0 0e 8d 06 07 00 0a 94
31 00 60 02 48 02 80 2f 80 01 8d 00 00 02 00 00
31 00 60 02 48 02 80 2f 80 21 8d 00 00 02 00 00
31 00 60 06 08 02 40 21 40 00 8d 06 48 00 48 02
31 00 60 06 08 02 c0 20 40 00 8d 06 88 00 48 02
31 00 60 06 08 02 c0 21 40 00 8d 06 58 00 48 02

2
src/intel/compiler/brw/tests/gen9/sendc.expected
View file

@ -11,7 +11,7 @@
32 00 60 02 40 02 00 20 80 0f 8d 06 01 00 0a 88
32 00 80 02 40 02 00 20 20 0f 8d 06 01 00 0c 8e
32 00 60 02 40 02 00 20 c0 0e 8d 06 01 40 0a 94
32 00 60 02 40 02 00 20 a0 0f 8d 00 00 02 00 80
32 00 60 02 40 02 00 20 a0 2f 8d 00 00 02 00 80
32 00 60 02 40 02 00 20 80 0f 8d 06 01 40 0a 88
32 00 60 02 40 02 00 20 20 0f 8d 06 01 c0 0b 8e
32 00 60 02 40 02 00 20 20 0f 8d 06 01 40 0a 8e