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intel/isl: Add the maximum surface size limit

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V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and
    2^38 bytes for gen9+.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit c07271fef0)
This commit is contained in:
Anuj Phogat 2017-05-19 12:09:22 -07:00 • committed by Andres Gomez
parent 7fc94625cc
commit 7bcb63457b
1 changed files with 22 additions and 0 deletions
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22
src/intel/isl/isl.c
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@ -1398,6 +1398,28 @@ isl_surf_init_s(const struct isl_device *dev,
base_alignment = MAX(info->min_alignment, tile_size);
}
if (ISL_DEV_GEN(dev) < 9) {
/* From the Broadwell PRM Vol 5, Surface Layout:
*
* "In addition to restrictions on maximum height, width, and depth,
* surfaces are also restricted to a maximum size in bytes. This
* maximum is 2 GB for all products and all surface types."
*
* This comment is applicable to all Pre-gen9 platforms.
*/
if (size > (uint64_t) 1 << 31)
return false;
} else {
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
* "In addition to restrictions on maximum height, width, and depth,
* surfaces are also restricted to a maximum size of 2^38 bytes.
* All pixels within the surface must be contained within 2^38 bytes
* of the base address."
*/
if (size > (uint64_t) 1 << 38)
return false;
}
*surf = (struct isl_surf) {
.dim = info->dim,
.dim_layout = dim_layout,