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i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.

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This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
(cherry picked from commit a01ba366e0)
This commit is contained in:
Kenneth Graunke 2017-11-16 22:31:27 -08:00 • committed by Emil Velikov
parent 093ae29b3c
commit 7bc213a644
1 changed files with 5 additions and 1 deletions
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6
src/mesa/drivers/dri/i965/brw_pipe_control.c
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@ -115,7 +115,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
brw_emit_pipe_control_flush(brw, 0);
}
if (devinfo->gen >= 8) {
if (devinfo->gen >= 9) {
/* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue:
*
* "Project: BDW+
@ -126,6 +126,10 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
*
* If there's a BO, we're already doing some kind of write.
* If not, add a write to the workaround BO.
*
* XXX: This causes GPU hangs on Broadwell, so restrict it to
* Gen9+ for now...see this bug for more information:
* https://bugs.freedesktop.org/show_bug.cgi?id=103787
*/
if (!bo) {
flags |= PIPE_CONTROL_WRITE_IMMEDIATE;