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radeon: Pass HEVC encode crop parameters to the encoder

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Signed-off-by: Thong Thai <thong.thai@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2351
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4184>
This commit is contained in:
Thong Thai 2020-03-12 10:05:48 -04:00 • committed by Marge Bot
parent 245f619411
commit 7b9414f23f
5 changed files with 49 additions and 10 deletions
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17
src/gallium/drivers/radeon/radeon_uvd_enc.c
View file

@ -60,10 +60,19 @@ static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.not_referenced = pic->not_referenced;
enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
(pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
if (pic->seq.conformance_window_flag) {
enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
} else {
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
}
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;

1
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
View file

@ -429,6 +429,7 @@ static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
? 0x1
: 0x0;
radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1);
if (conformance_window_flag == 1) {
radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_right);

17
src/gallium/drivers/radeon/radeon_vcn_enc.c
View file

@ -106,10 +106,19 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
enc->enc_pic.not_referenced = pic->not_referenced;
enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
(pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
if (pic->seq.conformance_window_flag) {
enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
} else {
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
}
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;

12
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
View file

@ -396,7 +396,17 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
(enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);

12
src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
View file

@ -137,7 +137,17 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
(enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);