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pan/mdg: Prefer type over regmode for schedule constraints

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Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5443>
This commit is contained in:
Alyssa Rosenzweig 2020-06-12 12:22:54 -04:00
parent 5cf5d3cc2d
commit 7ae2110e61
1 changed files with 2 additions and 2 deletions
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4
src/panfrost/midgard/midgard_schedule.c
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@ -198,12 +198,12 @@ mir_is_scalar(midgard_instruction *ains)
/* Otherwise, check mode hazards */
bool could_scalar = true;
unsigned szd = nir_alu_type_get_type_size(ains->dest_type);
unsigned sz0 = nir_alu_type_get_type_size(ains->src_types[0]);
unsigned sz1 = nir_alu_type_get_type_size(ains->src_types[1]);
/* Only 16/32-bit can run on a scalar unit */
could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
could_scalar &= (szd == 16) || (szd == 32);
if (ains->src[0] != ~0)
could_scalar &= (sz0 == 16) || (sz0 == 32);