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radv/amdgpu: Remove can_patch and chained submit code path.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
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parent
6aa518ea86
commit
7abd8c499b
4 changed files with 8 additions and 81 deletions
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@ -279,7 +279,7 @@ radv_queue_submit_empty(struct radv_queue *queue, struct vk_queue_submit *submis
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};
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return queue->device->ws->cs_submit(ctx, &submit, submission->wait_count, submission->waits,
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submission->signal_count, submission->signals, false);
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submission->signal_count, submission->signals);
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}
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static void
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@ -1750,7 +1750,7 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
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result = queue->device->ws->cs_submit(ctx, &submit, j == 0 ? wait_count : 0, waits,
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last_submit ? submission->signal_count : 0,
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submission->signals, false);
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submission->signals);
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if (result != VK_SUCCESS)
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goto fail;
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@ -1826,7 +1826,7 @@ radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
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.cs_count = 1,
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};
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VkResult result = queue->device->ws->cs_submit(ctx, &submit, 0, NULL, 0, NULL, false);
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VkResult result = queue->device->ws->cs_submit(ctx, &submit, 0, NULL, 0, NULL);
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if (result != VK_SUCCESS)
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return false;
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@ -294,7 +294,7 @@ struct radeon_winsys {
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VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx,
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const struct radv_winsys_submit_info *submits, uint32_t wait_count,
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const struct vk_sync_wait *waits, uint32_t signal_count,
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const struct vk_sync_signal *signals, bool can_patch);
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const struct vk_sync_signal *signals);
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void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
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@ -1876,7 +1876,7 @@ radv_shader_dma_submit(struct radv_device *device, struct radv_shader_dma_submis
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.cs_count = 1,
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};
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result = ws->cs_submit(device->shader_upload_hw_ctx, &submit, 0, NULL, 1, &signal_info, false);
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result = ws->cs_submit(device->shader_upload_hw_ctx, &submit, 0, NULL, 1, &signal_info);
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if (result != VK_SUCCESS)
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{
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mtx_unlock(&device->shader_upload_hw_ctx_mutex);
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@ -945,75 +945,6 @@ radv_assign_last_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_reque
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request);
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}
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static VkResult
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radv_amdgpu_winsys_cs_submit_chained(struct radv_amdgpu_ctx *ctx, int queue_idx,
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struct radv_winsys_sem_info *sem_info,
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struct radeon_cmdbuf **cs_array, unsigned cs_count,
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struct radeon_cmdbuf **initial_preamble_cs,
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unsigned preamble_count, bool uses_shadow_regs)
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{
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struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
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struct radv_amdgpu_winsys *aws = cs0->ws;
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struct drm_amdgpu_bo_list_entry *handles = NULL;
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struct radv_amdgpu_cs_request request;
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struct radv_amdgpu_cs_ib_info ibs[1 + AMD_NUM_IP_TYPES];
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bool enable_preemption = cs0->hw_ip == AMDGPU_HW_IP_GFX && uses_shadow_regs;
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unsigned num_handles = 0;
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VkResult result;
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for (unsigned i = cs_count; i--;) {
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struct radeon_cmdbuf *cmdbuf = cs_array[i];
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radv_amdgpu_cs_unchain(cmdbuf);
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if (i + 1 < cs_count) {
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radv_amdgpu_cs_chain(cmdbuf, cs_array[i + 1], enable_preemption);
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}
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}
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u_rwlock_rdlock(&aws->global_bo_list.lock);
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/* Get the BO list. */
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result = radv_amdgpu_get_bo_list(cs0->ws, cs_array, 1, NULL, 0, initial_preamble_cs,
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preamble_count, &num_handles, &handles);
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if (result != VK_SUCCESS)
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goto fail;
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/* Configure the CS request. */
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if (initial_preamble_cs) {
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for (unsigned i = 0; i < preamble_count; ++i) {
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ibs[i] = radv_amdgpu_cs(initial_preamble_cs[i])->ib;
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}
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}
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ibs[preamble_count] = cs0->ib;
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if (uses_shadow_regs && cs0->hw_ip == AMDGPU_HW_IP_GFX)
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ibs[preamble_count].flags |= AMDGPU_IB_FLAG_PREEMPT;
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request.ip_type = cs0->hw_ip;
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request.ip_instance = 0;
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request.ring = queue_idx;
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request.number_of_ibs = preamble_count + 1;
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request.ibs = ibs;
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request.handles = handles;
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request.num_handles = num_handles;
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/* Submit the CS. */
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result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
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free(request.handles);
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if (result != VK_SUCCESS)
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goto fail;
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radv_assign_last_submit(ctx, &request);
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fail:
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u_rwlock_rdunlock(&aws->global_bo_list.lock);
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return result;
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}
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static VkResult
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radv_amdgpu_winsys_cs_submit_fallback(struct radv_amdgpu_ctx *ctx, int queue_idx,
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struct radv_winsys_sem_info *sem_info,
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@ -1377,7 +1308,7 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
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static VkResult
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radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx,
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const struct radv_winsys_submit_info *submit,
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struct radv_winsys_sem_info *sem_info, bool can_patch)
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struct radv_winsys_sem_info *sem_info)
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{
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VkResult result;
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@ -1389,10 +1320,6 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx,
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result = radv_amdgpu_winsys_cs_submit_sysmem(
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ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
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submit->initial_preamble_cs, submit->continue_preamble_cs, submit->uses_shadow_regs);
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} else if (can_patch) {
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result = radv_amdgpu_winsys_cs_submit_chained(
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ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
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submit->initial_preamble_cs, submit->preamble_count, submit->uses_shadow_regs);
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} else {
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result = radv_amdgpu_winsys_cs_submit_fallback(
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ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
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@ -1406,7 +1333,7 @@ static VkResult
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radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
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const struct radv_winsys_submit_info *submits, uint32_t wait_count,
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const struct vk_sync_wait *waits, uint32_t signal_count,
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const struct vk_sync_signal *signals, bool can_patch)
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const struct vk_sync_signal *signals)
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{
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struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
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struct radv_amdgpu_winsys *ws = ctx->ws;
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@ -1470,7 +1397,7 @@ radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
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.cs_emit_signal = true,
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};
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result = radv_amdgpu_winsys_cs_submit_internal(ctx, &submits[0], &sem_info, can_patch);
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result = radv_amdgpu_winsys_cs_submit_internal(ctx, &submits[0], &sem_info);
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out:
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STACK_ARRAY_FINISH(wait_points);
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